How to tell the PCB DRC that the connector is in fact a wire?

Re: your GitLab issue.

You have two separate PCBs so should really have two separate projects . . . if you really don’t want to do that then simply have 3.3V 3.3V-1 and GND GND1 (or some similar naming convention) that will keep the PCBs apart.

(I just read up the thread and see something similar has already been suggested . . . I don’t see any issue here, 2 PCBs = 2 Projects or do a work around to bend KiCad to you will)

What now is ‘by default’ can, may be changed in future and can be useful for some users.

One my design has two PCBs. One is module (uC + Flash + EEPROM + RTC) standing vertically at the other.
I can’t count how many times I’ve changed the order of signals on the 40-pin connector. I would have nothing against if KiCad could control that I didn’t made mistake during it.

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I respectfully disagree. The original use case (which was simplified to illustrate the point) is one circuit divided over several planes. It is simulated and checked by the electrical design rule checker as one circuit as well. And, there is not only power, but a lot more lines are connected over the hierarchical sheets by connectors as well. As said before, for any issue there is a hack to solve it, that is not the point. You could even use Gimp to draw the PCB. In my post I put forward a situation I encountered many times now over the eight years I use KiCad.

If it turns out I am the only one in this situation, great, nothing to see in this theater. Otherwise, my use case and the improvements it may lead to for KiCad could be beneficial to others as well.

In your first post you said . . .

So it is actually two PCBs . . .

But OK, you want to make two PCBs in one to save cost, I can understand that, couldn’t you simply make a footprint containing both connectors and have two pad 1s and two pad 2s ? I’m pretty sure pads with the same number are linked.

I think the idea of a user layer with wires has merit. However, when you guys make a feature request make it as easy as possible to do. Dont overload it with all kinds of goals. just say for example

  • Make it possible to have conductive wires on user layers.

or

  • Make it possible to mark copper layer as non fabrication layer.

This makes removes the burden of the developer and is much more actionable.

TBH, I think this feature request should be put at the bottom of the pile.
All the tools are present right now to do this - all it takes is assigning wires to a user layer, and then just unchecking a box when it’s time to output Gerbers.
Spending developer time to make KiCad into some fetish hobbyist ancient PCB duplication program is misdirected energy.

I am unable to draw wires on user layers, how do you do that?

Anyway the issue is that if the file is shared by people. Thing that non hobbyists do then there might be a mistake. Just allowing me to tag layers as non outputting would solve that. And this is a really trivial change as far as development is concerned.

No comment on priority. Priority is decided by the people who do the work.

No comment on usefulness. People either find features useful or not. Does not means that if you find a thing useless that you could have gained something that you do find useful with same resources.

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From experience, that statement is usually incorrect. What can seem like trivial changes on the face of it can be very involved, or have wider consequences, than appear on a superficial inspection.

Yes, two PCB’s, but one project.

Indeed, I place the two PCB’s together since it is cheaper and quicker to produce. Cheaper because my manufacturer has a fixed setup cost per project. Quicker because I do not have to go through all the menu’s and numerous production settings twice.

Well, I have tried this, but encountered some hurdles.

  • For my example a footprint is needed with four pads (two pad with number 1 and two with number 2. The symbol must now contain two units, one for each connector. So far so good, you can place each unit on a separate sheet.
  • On the PCB you now have one footprint, and you must move two pads from the designed location to the actual location, the footprint is ripped apart so to say. See Image.
  • After the connections are made, the errors remain. The pads with equal numbers seem to be seen the same net (which was already the case, due to the power symbols), but are now forced to be interconnected. (Was that not the point of issue #15999 ?)

Most likely I made a wrong turn somewhere. This is possible since I moved over from KiCad 5 directly to KiCad 8 only recently. Surely you have tested this suggestion before you made it. How should I proceed?

Why not draw your schematic as A below is drawn?

It is obvious how the two parts are connected.
B, I think, shows how how a chasis mounted pot is connected to a circuit. The only difference between A & B being J4 & RV1 are “exclude from board” in their properties.
A gives a two board layout as below ( green lines are the ratlines):

ksnip_20241004-125642

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Yes i have noticed that your codebase is a bit too tightly coupled. The signs are all over the forum and codebase.

Anyway, you are saying adding metadata to a layer is a complicated effort. That may be, but shouldn’t.

This is a common reality of large software projects that have been in development for a long time. KiCad was released over 30 years ago - that’s a lot of evolution in software design terms.

I’m saying nothing of the sort. Adding metadata would be pretty simple. I’m saying there are likely other functional couplings that make ‘trivial’ changes non-trivial (and I’m not talking about how tightly or not the codebase is coupled). In this instance, things to consider could include:

  • Is this a user (non-copper) layer that we pretend is copper, or a copper layer that we get the other tooling to ignore? The answer to that strongly influences the following:
  • The stackup manager - add one hidden copper layer, currently you’d get two as that’s how PCBs are built
  • The router - if it’s a non-copper layer, the router currently will ignore it
  • Length tuning - are these real traces? Should they be included? What about the vias linking to this layer?
  • 3D rendering / export - we use internally, and can export, 3D copper models. What do we do for these layers, and for other copper objects transiting through them?

There are probably others, but those are what immediately spring to mind.

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Thank you for taking the time to make this example. It is however addressing an other situation since the nets of both sides of the connector are not coupled if I interpret the drawing correctly. In that case there is no problem with the DRC of course.

My 2 cents, here is how I do similar stuff. I do have a lot of project with multiple PCBs in it, mainly to create the board and the related front panel.

I don’t use power symbol, but I use global label symbol.
And I use different name for the global label used for the front panel,
for example GND, GNDf or 5V, 5Vf (f is for front panel). and similar for my signal pins that goes trough the connector between my main board and my front panel.

I still quite easy to read, and it create 2 different net.
So it’s OK for DRC. But if you use the simulation tool then it’s not working.

Finally I use the kikit plugin to split the board and generate independent gerber for production.

Note : a footprint with 2 parts, will have a rastnet drawn between the the 2 pads with the same number. as Kicad don’t suppose that the 2 pads are in fact connected outside of the board. Most of the time that is the proper behavior. For example a MCU footprint with many Vcc and Gnd pins, where you are supposed to connect each of the power pin to the board with the proper local decoupling.

True, but they are connected with a two pin plug and socket. Kicad PCB Editor does not support tracks (or wires) off the board. Kicad only supports what is on the PCB. You have to rely on the Schematic to show off board connections.

@bertrand_meneroud posted the lack of support for off board comment first. That’ll teach me to get another coffee half way through answering a post. :slightly_smiling_face:

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another issue with using a non fabricated layer to show these “wire” is that you will still get a DRC error when crossing the board edge cut to reach the other board.

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@devlaam

My “B” example shown above uses similar reasoning to your two board problem. Ask yourself: how do you support the pot. on the PCB when that pot. it is not on the PCB?

I think this is not an adequate example as you don’t give all MCU GND pins the same number.

About just assuming that pads in footprint with the same number are connected outside of PCB (like in many tact-switches or 3 pin coin batteries) I was writing in 2019:

but was told that there are some very important reasons (that are out of my understanding) to not assume that.

I think this is rather free advantage than a problem to be solved. If someone using non-copper layer will be able to mark that pads are connected outside PCB than router should practically ignore it. Such connection need not to be avoided with other tracks, need not to have clearance from any other copper (tracks/pads), can be ignored while zone is filled.
I didn’t follow the topic and I don’t know if the problem of really 2 net, but 4 pad tact-switch has already solution or still is a problem (using extra (not manufactured) copper layer can be a solution for THT tact-switches, but for SMD not).
Having a way to mark at non-copper layer in footprint that pads are connected outside PCB can be also a solution to this problem and will allow to make KiCad not insist on connecting at PCB pads that are already connected in tact-switch allowing to go with other tracks under it what is probably needed when making matrix keyboards.

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