How to set clerance and zone settings for tracks and vias

Specifically, what I’m trying to do is set a track so that it does not connect to a copper zone (of the same net). One can do this for pads (in the Pad Properties dialog, under the “Local clearance and settings” tab — set “Connection to copper zones → Pad connection” to “None”), but not for tracks or vias.

I can’t seem to find this feature in KiCAD (version 5.1.2). And I can think of one legitimate use-case for it: decoupling capacitors placement when one needs to use the top layer as the ground plane (or Vcc plane).

See image below:
If the ground plane is on a different layer, no problem. If the ground plane is on the top layer, I don’t want the plane to touch the GND pin of the IC (not a problem, I can set zone settings for pads!!), or the track that goes from the IC pin to the decoupling capacitor pin (a problem — this requires a “Connection to copper zones” setting of “None” for the track).

If it is possible, how do I achieve this?

If not: is this an already-requested feature? Are there plans to implement it in the near future?


Have you pressed the “b” key on the keyboard?

He specified it is about preventing a connection to the same net as the trace/via. Pressing b will not help here as it only takes into account what kicad is capable of doing.

In KiCad you will need to use net-ties to achieve this. They are however not implemented as a special tool. There are however special symbols and footprints available as a workaround. (Better options are worked on for version 6)

Place the net-tie in your schematic between the parts you want to isolate and the net you want to finally end up connecting to. In pcb_new place the corresponding footprint at the place where you want the two nets to connect.

As @Rene_Poschl says net-ties are probably the best solution at the current state of art for KiCad. But it isn’t the only method.

Another way would be to add a keepout for zone fill around the pads/traces where you want isolation from the zone. This is a quick and dirty method, and becomes annoying if you move things around because it is now Yet Another Feature that you have to remember to move.

I’m no engineer so I don’t know if it is absolutely necessary to do this, or if just having the capacitor attached to the zone immediately adjacent to the pin being filtered is sufficient.

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In most situations it’s very useful to have the associated Zone (a.k.a. “filled area”; a.k.a. “copper pour”, a.k.a. “copper plane”) make the connections automagically. Therefor, it’s not a significant burden to deal with the exceptions on a case-by-case basis.

Select the pad, then press “E” (for “Edit Pad Properties”)

Activate the “Local Clearance and Settings” tab. Find the “Copper Zones” parameters, and set “Pad connections” to “None”.

NOW press the “B” key!


The user is aware of this. It is after all mentioned in their question. What they ask is if there is a similar option for tracks and vias. (Answer: Not really.)

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Oops . . . . you are correct. (My apologies to @cal-linux .)

He mentions it twice. I don’t know why I missed his real question about the traces and vias. Maybe too many other things on my mind tonight.


I would like to ask: under what circumstances this is really needed? In about all datasheets of ICs they show planes/zones/pours connected to pads of the IC and the capacitor. Only under some special circumstances there would be need for trace only connection between two pins. It’s important that the impedance between the IC and the capacitor is smaller than the impedance between those and other components. And even that is really important for only the smallest capacitor.

Provided that the components are close to each other, as they are in your picture, it should be enough to set the pad-zone connection setting for both pins, of the IC and of the capacitor, to “no connection”. The zone clearance takes care of the rest - it probably doesn’t get connected to the trace between the IC and the capacitor. It doesn’t work for the via, though. But on the other hand I don’t understand why you would need that in this situation. If the plane is on the top side, it’s better to connect directly to it.

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I would also do this with net-ties, as mentioned befor.

Connecting the IC directly to the GND plane will have lower impedance, but the tradeoff is that more switching noise from the IC itself is coupled into the GND & Vcc planes.

Some time ago I read an article which suggested this method, and even used a longer track (1 to 2 cm) between the decoupling cap and the GND / Vcc planes to add a little more induction, so these planes are even kept cleaner.

This is probably most usefull in a mixed design with analog and digital circuits close together.

This is unfortunate. It works, but with significant additional work, and with some unavoidable quirks/downsides.

Well, all of the above boil down to the net-tie footprint, so I guess I could just go ahead and create custom net-tie footprints.

Correct me if I’m wrong: these are some of the downsides the way I see it:

  • Net-tie footprint shows several things in the silk and fab layers (a little bit of work to make those invisible on a per isolated connection basis). Not terribly bad.
  • Net-tie footprint has a silkscreen frame/perimeter that cannot be removed. If this overlaps with pads in the IC, one can compensate for this when plotting. But still, it will show an ugly/distracting blob of silkscreen lines next to the pads involved.
  • Thinnest net-tie footprint is 0.5mm — for an IC at 0.5 or even 0.65mm pitch, the pads are significantly thinner than this, so I cannot make the net-tie footprint overlap with the pad. (and I most likely won’t want to put it farther away — the net-tie is already very long)

Ultimately — I think it would be so much easier to just have the ability to specify clearance and zone setting for tracks and vias. It would also increase consistency: if it can be done for some copper objects in the layout, why not for all copper objects? (well, with whatever exceptions as applicable)


Copy an existing footprint into your own library and modify it. I have several net tie footprints for different situations. Naturally it doesn’t need anything else than copper.

As was said, in 6.0 we will probably have “native” net ties: as far I have understood the discussions, you will be able to use a track or a via as a net tie. And this will probably be somewhat easier to use than the current symbol/footprint net tie system.

I agree that “no zone connection” option would be the easiest solution to use and it might even have some other use cases. You can of course file a bug report for the feature wish. But it would need a file format change and wouldn’t be available until 6.0 anyways.

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Hahaha — no worries! It is in fact a bit refreshing, occasionally seeing an oversight/mistake like this… you know, it confirms that it is actual human beings responding in the forum! (although sneaky tech support companies using AI / bots to pose as tech support people that care about you, or dating websites putting up AI / bots posing as females interested in dating, in the future will design those AI’s to occasionally “make mistakes” … :-\ oh, we’re doomed!! :slight_smile: )


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