I am looking for the right way to design a 0.5mm pitch BGA [1] footprint (XC7A35T package) on a 6-layer PCB.
I am trying to route BGA package but i am unable to routing. So what setting should change in routing to make routing possible for me.
i attaches screenshot of my BGA pacakage.
Thank you
The small circles are the pads themselves, while the bigger circles define the clearance where no copper from conflicting nets is allowed. Clearance is normally specified in the netclasses. Are you familiar with those?
For generic advice for breaking out the tracks from a 0.5mm bga, a simple search gives more and better answers then you could expect from a forum like this.
“XC7A35T” is a Xilinx part number, not a package. Based on the ball pitch I’m guessing the package is probably CPG236 (this part comes in other packages, but only one with a 0.5mm ball pitch).
This is important because there is a difference between BGA breakout for a package with many dense balls and one with gaps in the pinout. For example, here’s the map of the CPG236:
With the open area in the middle of the grid, you only have to route at most three deep before reaching an open area. This will make it far easier to route with fewer layers than one where there are no gaps in the ball grid.
I suggest you refer to AMD’s 7 Series FPGAs Packaging and Pinout Product Specification User Guide (UG475).
I would also suggest discussing manufacturing capabilities with your PCB fabricator. JLCPCB now does filled and plated via-in-pad for free on their 6-layer boards. This sort of technology might make it much easier to route a BGA.
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