Hi world,
I’m using kicad “Version: 9.0.0, release build”
I have trouble with “74xGxx:74LVC2G02”, this part override my “VBat” netname and set it to “VCC”, but it’s not “VCC”, it’s “VBat” ! … frustrating …
The schematic DRC send me a warning about “VCC” / 'VBat" connected to same net, and “VCC” as been selected as uniq netname.
→ how to manual select “VBat” as net-name ?
(or better : how to always prefer MY netname over part’s pin netname ?)
It’s either coming from the pin name . . . what is the pin name ? or that pin is connected to VCC elsewhere . . .
Is that a custom symbol ? is it correct ?
You can right click the track, goto Properties and then change it’s Net to VBat
Yes, I think too that “VCC” come from symbol pin name :
And no : the pin is not connected to VCC elsewhere, the symbol pin-name just override my net-name.
It’s not a custom symbol, it’s from official the library “74xGxx”.
… but strange : looks like this device is not anymore in kicad 9 ?
I have to double check this point.
Overriding a netname with the pinname is (was) a feature of power symbols.
But normally for this feature the symbol must be specifically defined as power symbol (in the symbol editor).
Just looked into this issue and it seems that alone the definition of a pin as Power Input already is enough to override the netname:
This looks like a bug - could someone give a second (third) opinion?
example:
forum_pin_power_input.zip (53.4 KB)
picture:
@Seb.26 : as a current workaround:
I’m not using V9 yet.
But if pin being PowerInput is enough to overwrite net name it have to be a bug, or there is may be some new conception and may be for example IC supply pins no longer are expected to be PowerInput.
Some microcontrolers have separate pins for Analog supply, Internal Digital Supply, Digital I/O buf supply.
I give each of them another name but in most cases connect all them together.
I see in V9 it will be generating by default Warnings.
I have checked - in my digital 1G 2G symbols I used Passive as supply pins. I sometimes supply CMOS gates from uC output pin.
I think the requirement of being defined as power symbol was added explicitly to remove the implicit confusing behaviour. But I may be wrong.
I have now looked into the documentation and into older kicad evrsions as well and the behaviour is correct and follows the manual:
hidden power input pins implicitly define the netname. The flag “power symbol” is not relevant for this behaviour. (manual section " Hidden Power Pins").
The hidden power input pin = global is the legacy behavior, it always has existed specifically to support these specific symbols. I agree that it is not optimal though.
I stumbled over this too, because it caused issues on my board. Opened an issue for this, but it was sadly closed because of “legacy”.
and this thread: Implicit Connection due to Hidden Power Pins
As I understand from this thread it is not new ‘feature’ and it was also in previous versions.
I don’t run ERC so I don’t care about any warnings there.
But I have never (since V4.0.7) noticed anything unusual with power net names. In ICs I’m using Power Input pins with many different names. For example my EFM32GG128B410F1024GQ64 has Power Input pins: “AV”, “IV”, “DV”, “VB”, “G”. But at PCB I see VCC and GND.
Isn’t it so that name of Power Input pin of Power symbol has precedence over name of Power Input pin from symbol being not Power symbol.
If it were such than it would explain why I didn’t noticed any problem ever.
I started with KiCad in a similar version and I also never noticed this. Until I started making custom symbols with stacked pins. This only happens if you set it to invisible and a power pin
Good to know, but I don’t plan to stack power pins. As practically for each power pin I use separate blocking capacitor I like to see it at schematic.
understandable. For MCUs I like to stack them and add these caps anyway. You’re right though, it is then kind of hard to see in the schematic
Our standard (before EMC our PCBs were designed by someone else) was to have GND pins at symbol bottom, VCC at top and I/O ports distributed at both sides. As practically I connect all I/O pins to bus then bus were going under symbol from one side to the other.
Additionally placing capacitors at top was not so easy.
Recently I was drawing some symbols for not very lot pin microcontrollers and I decided to have top and bottom free from pins. I/O at right, supply, reset, XTAL on the left. VCC pins with some distance between them so capacitors can be one to one.
