How to remove copper pour on PADs near each other?

Considering a resistor connected to GND in the following image, which is the same net used on copper pour. How can I configure the filled zone to remove the unnecessary horizontal trace that goes towards PAD 1?

I don’t think the thermal relief generation algorithm removes islands yet. You could place a keepout between the pads if it is critical to remove them. This should probably make it in to the bug tracker at some point, since I think it would be nice for the pour algorithm to remove thermals that just end in an isolated island like that.

Edit: I reported this as https://bugs.launchpad.net/kicad/+bug/1741265

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In most cases I think this situation has no impact on electrical behavior or performance, but it DOES look ratty. Sometimes you can turn islands or peninsulas into connected regions by decreasing the minimum track width inside the zone. Take it all the way down to 6 mils (0.15mm) or whatever minimum feature size your fab house supports and see if that helps. I have fiddled with little keepout zones, or laying down thin traces across the gaps so they appear to have been bridged by the zone filling algorithm. Both of these approaches take a disproportionate amount of time and effort compared to the benefits achieved, and need special attention after you move ANYTHING in the area of the island.

Dale

@craftyjon thank you. The bug report is a good idea since I have many of these things to fix them
manually.

@dchisholm good. My concern is the impact of that on manufacturability/assembly which I believe that could be an issue.

This should not be an issue for a modern fab/assembly process. I could see it being annoying if you are milling the board yourself, though.

Actually for modern SMT assembly, thermals are not needed at all. They make rework easier if you don’t have a preheater, but I recommend getting a preheater and turning off thermals since they are bad for pretty much every reason except ease of hand soldering.

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You can get optimized from some professional pcb manufacturers I think.

maybe it’s not a problem when they are soldered in a oven, but before this process we need to make prototypes, I have an issue with that thing in this board:


hand solder that resistor a couple of times and a short will appear on one of the terminals, or a leak though the flux, difficult to clean (because the paint of the solder mask can’t hold that much)
it should be a more easy way to trim this islands instead the need to add dozens of keep-out areas

I wonder what algorithm could be applied to remove these small pieces, it might be obvious to a human which pieces are not needed, but it doesn’t sound like an easy thing to code.

The only algorithm that comes to mind would be a tic off for "no fill below footprint of size X or smaller? That would be a refinement of the clearance tolerance.

As this hasn’t come up before I don’t know if it would be a high priority for the coders unless it is really easy to implement.

The main problem now seems to be clearance with regards to solder mask being adequate for hand soldering?

In prior incarnations, the problem with islands and peninsulas under SMT passive components (especially 0805 and 0603 sizes) was addressed at the footprint level: the in-house footprint had a built-in keepout zone under the center of the part. The downside was that you could not run a trace beneath the part; since KiCAD lets you customize keepout zones to prohibit either traces, or copper pours, (or neither), traces could be allowed while prohibiting copper pours. The new downside is that ALL copper pours would be prohibited, not only the ones that create isolated islands and peninsulas.

Dale

I don’t own a microscope, so the picture is not the best:


but you may see the reflection of the naked border of the island under R57, the coper is 2oz, and some times this can make a contact (which is easy to detect) and other times it can become a leak through the flux, the flux under the resistor is also no easy to clean.
I guess, when this is properly soldered in a oven it’s not a problem, but in the prototype stage when I need to tune the parts, this becomes an annoying thing.

The only algorithm that comes to mind would be a tic off for "no fill below footprint of size X or smaller? That would be a refinement of the clearance tolerance.

This is a possibility, but I think a more generic case could be something like ‘if this filled extension don’t reach the end of the zone, delete it’, don’t know if such thing is too difficult to code tho. :smirk:

Perhaps looking for neck-down areas in the fill that are smaller than a specified minimum, and then checking if the fill is a peninsula on either side of the neck-down.

One bug in thermal spoke removal has been fixed, so this behavior should be better in nightlies going forward. Please report any other zone filling issues you notice.

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