A (rather imprecise) description of Craig’s objective is to achieve “tighter electrical coupling between (CAT501, Pin 5) and capacitor C501”, than between " (CAT501, Pin 5) and the general power plane". This assumes that the power plane conducts stray currents and noise voltages, and system performance can be improved by forcing CAT501 to draw its switching currents directly from C501 rather than the general power plane.
The arguments for this kind of scheme for power distribution and decoupling are similar to the arguments for “star ground” connections.
I am not in a position to debate the technical merits of this idea.
I don’t think I have seen a PWB layout program that implemented this idea in a clean, straightforward, manner. The only approach I can suggest is to create an “electrical tie point” component, and assign a footprint such as “NetTie-I_Connected_SMD” from the “Oddities.pretty” library. Then create an isolated net containing 3 nodes: (CAT501, Pin 5),
(C501, Pin1), and (Tiepoint, Pin1). Connect (Tiepoint, Pin2) to the “+3V3” power bus.
I think you are wanting a “thermal relief” area for your power pins, not a “keep out area”. @devbisme mentioned how to do that: https://forum.kicad.info/t/how-to-properly-handle-power-gnd-pads-on-power-gnd-planes/6972/2?u=dchisholm
Edit the “Properties” of your fill-zone to get the amount of separation you want.
I think you can also set this on a pad-by-pad basis in the Footprint Editor.