How to properly handle power / gnd pads on power / gnd planes


Hey Everyone,

Here is what I am trying to figure out. I am working on a PCB layout where several components that I am using require some filtering caps to be placed between 3.3 and ground. After adding my power and ground planes to the board, I am trying to wire up those components to their capacitors, but I am running into an issue with the power plane. First a picture.

As you can see pin 5 is the power plane, but I need to add some keep out or whatever to make the footprint of pin 5 isolated from the power plane, so I can wire in the cap next to it. Think this is a pretty standard feature, what do I need to change on pad 5?



It looks like you need to set the thermal relief for the power plane to something greater than zero. Your pin 5 will still be connected to the power plane (as it should be). You can then put the bypass cap near pin 5 and make the connection to ground (the +3.3V pin of the cap will attach to the power plane automatically, just like pin 5).


The problem is you need to layout tracks then fill the power planes. It’s ok to set up the zones, but no need to fill until you have finished layout.

To continue routing, just turn off zone display and place your tracks. Then turn on the zone display and do “Fill all zones”.


Hey Bob,

Thanks for the details but wierdness continues. I did what you suggested and stopped the zone display and ran the trace and then reenabled the zone display and hit ‘B’ for fill all zones.

And then I reenabled the zones and filled them, but.

No keep out areas anywhere! Any thoughts?



Why do you need a keepout? Pin 5 is connected to pin 1 of the cap via the power plane.


Why the large distance between the IC and its capacitor. Shouldn’t it be placed as close as possible to it? (Assuming C501 is the Capacitor fo CAT501)


A (rather imprecise) description of Craig’s objective is to achieve “tighter electrical coupling between (CAT501, Pin 5) and capacitor C501”, than between " (CAT501, Pin 5) and the general power plane". This assumes that the power plane conducts stray currents and noise voltages, and system performance can be improved by forcing CAT501 to draw its switching currents directly from C501 rather than the general power plane.

The arguments for this kind of scheme for power distribution and decoupling are similar to the arguments for “star ground” connections.

I am not in a position to debate the technical merits of this idea.

I don’t think I have seen a PWB layout program that implemented this idea in a clean, straightforward, manner. The only approach I can suggest is to create an “electrical tie point” component, and assign a footprint such as “NetTie-I_Connected_SMD” from the “Oddities.pretty” library. Then create an isolated net containing 3 nodes: (CAT501, Pin 5),
(C501, Pin1), and (Tiepoint, Pin1). Connect (Tiepoint, Pin2) to the “+3V3” power bus.

I think you are wanting a “thermal relief” area for your power pins, not a “keep out area”. @devbisme mentioned how to do that:
Edit the “Properties” of your fill-zone to get the amount of separation you want.

I think you can also set this on a pad-by-pad basis in the Footprint Editor.



I think you may be over-reading, I think craig is probably a bit new to layout (nothing wrong with that). CAT501 is a serial EEPROM, not super high-speed stuff. As always it’s a bit difficult to judge when we can only see two components.

I’d take a step back and ask why use a power plane for 3.3V?


Faster way for making screenshots in ubuntu :wink:


think craig is probably a bit new to layout (nothing wrong with that).

That’s putting it mildly :slight_smile: . Ive only laid out one board that I had manufactured, so this guy would be number two.
In reading the various feedback, it would seem that I should place the cap nearest the power pin. And i should be off to the races.

Thanks much