I’ve not found any way to place micro-vias between two inner layers (as would be needed for stacked micro-vias). I’ve resorted to using a buried via as a work-around, as I think the Gerber and drill output for this buried via will be identical to that of a micro-via. Is there a cleaner way to place intra-inner-layer micro-vias? I’m not using skipped micro-vias (connecting layers 1 and 3 while skipping 2, for example), but I think this work-around would work for skipped micro-vias as well.
Maybe you need to allow blind and buried vias in the Design Rules -> Global Design Rules.
From wikipedia:
“IPC standards define microvias as blind or buried vias with a diameter equal to or less than 150 μm”
Blind and buried vias are already enabled in my setup, otherwise I couldn’t use the workaround I described. Micro-vias are typically different than ordinary blind or buried vias by more than just size. Micro-vias are copper-filled, whereas in general, blind and buried vias are not. Kicad already differentiates blind vias from micro-vias, so it seems to me that it would make sense to differentiate buried vias from micro-vias between inner layers.
I needed stacked microvias last week and I just told the manufacturer that all microvias (0.15mm) should be laser cut, resin filled, copper tapped (via-in-pad) and should go through all layers.
That board didn’t need a variety of regular microvias and buried vias, it just needed the stacked ones so I told them so and they are in production.
Sorry Steve,
I meant micro vias in Design Rules. With Crtl-V a micro via is placed while routing a track.
No worries, Pedro. Yes, microvias are enabled in Design Rules. Microvias (or cntrl-v) work when routing from an outer layer to the next layer down, but not between inner layers (the option for microvias goes away in the routing menu). I intend to take a similar approach to the one taken by Marcos, and just tell the fabrication house to differentiate between types of vias by size. I’ve checked the results of “microvia” vs “blind via” in the Gerber files, and there’s no distinction anyway, so it’s necessary to communicate via type to the fabrication folks anyway (unless they use the .kicad_pcb file directly).
It looks like this is just an issue of how “microvia” is defined. In Kicad, it seems to be only from an an outer layer to the adjacent layer. I see now in the PCBnew manual, “Micro Vias, like buried vias but restricted to an external layer to its nearest neighbor.” Something for the user’s manual suggestion box is to elaborate on how buried vias should be used for intra-inner-layer micro-vias.
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Hi,
I ran into the same problem trying to route stacked vias. I played around a little bit with the KiCad source. The constraint of allowing micro vias only from outer layer tho the one below is to strict. But KiCad had no way of knowing how many layers deep one can put micro vias.
I enhanced the way vias are handled by pcbnew. If you want you can test the new functionality. It would be great to hear what you guys think of it.
I wrote a blog post about it: http://www.kurzschluss-blog.de/2017/09/kicad-improved-via-management.html
It is not finished, but it is usable enough if you know what you are doing.
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