I’m trying to figure out how to properly lay out a footprint for an RJ45 jack which has a pad that contains part of an NPTH cutout. I found an existing footprint for this jack, but the pad was modeled as a graphic rectangle, which stopped the DRC from finding a trace that had mistakenly wandered onto the pad, rendering a batch of boards useless. I’d like to lay out this footprint properly to avoid this mistake in the future. Is there a better way to do this? I started to mess around with the custom primitives, attempting to draw a pad with segment and arc primitives, but the arc primitive is exceedingly hard to work with (and has some fields swapped in its dialog box), making everything confusing and rather unusable. A screenshot of the datasheet is attached–I’d love to hear about everyone’s workarounds.
After some finagling with the polygon tool, I did find a way to make something sorta similar. If anyone has a better way of doing it beyond adding a large number of extra points to the concave part of the pad, I’d love to hear it! If any devs are watching–it would be really nice to be able to subtract primitives from a pad–that would make this whole process much easier.
Alternatively you can use a polyline and an arc as part of the pad shape. Fill the inside with a graphic polygon. As long as the edges of the outside lines and the edges of the graphic polygon intersect another the footprint editor can make it one continuous pad. Merge them as explained above. Place an NPTH right next to the arc.
I advice against using plated through hole in this case. A plated through hole with copper size smaller than the manufacturers required annular is undefined. (Your manufacturer can either try and make a plated hole which depending on tolerance combinations could result in there really being a partially plated hole or they notice it and convert it to unplated. If you design it using unplated in the first place then it is in a separate drill file so it is always well defined.)
This may also lead to endless conversations between you and the manufacturer (Chinese? It would certainly make it easier… ). They want to know what you really want, a plated hole, non-plated or semi-plated (castellation, which may be impossible with a small hole). If you want to leave clearance between the NTPH and copper you should rather make it so.
I should warn, If copper touches the hole, most board houses will produce it as a plated through hole by default.
If you want un-plated, you have to leave a separation gap.
Found this out on a previous project the hard way, that plating really sticks to the hole walls far better than I was aware, and as such was a pain to un-plate the holes.
I would assume only board houses that want a combined drill file for both. Because if you have different drill files then you do not need to use this hack to determine which hole should be plated.
I’ve been caught by it twice in the past, where they just combined both drill files. The only reliable way I have found for all cheap board houses to leave a hole unplated is to mark it as a edge cut circle, but that is ugly…
If in doubt contact your PCB fab ahead of time… but just covering all bases, if they combine the files and there is copper touching at least 1 side, they may plate it, If there is no copper, they may leave it be. and if it absolutely must be unplated, and you can’t wait for a reply, you can use the edge cuts trick.
I’ve spent another hour on this, and the only way I can get the pad addition method to work is if the through hole is plated. I did have some concerns about tolerances after through hole plating, and agree that the holes should be non-plated ideally. Unfortunately, it seems that I can’t assign a pad number to an NPTH, so whenever an NPTH intersects the SMD pad the DRC throws an error. I’ll switch back to my “good enough” design with clearances.
If an option existed for subtracting graphic items from each other, this would be an incredibly easy task
FYI, when you specify a plated through hole you are specifying the finished hole diameter. The board manufacturer knows the plating thickness of their specific process and will choose a drill size appropriately. If your manufacturer insists that all holes are specified to the type of drill they use and you have to know their through hole plating thickness, then they are in the minority and are expecting you to know more than necessary about their manufacturing processes.
I have always defined NPTH as having pad size much smaller than drill size.
I remember than reading KiCad documentation (when 4.0.6 was current) I have read something that if drill size equals pad size then it is NPTH. I assumed from that that KiCad when generating gerbers masks copper layers with drills. But at Thursday I ordered my first V5 PCB and noticed that it is not masked.
I’ve got info (from my contract manufacturer) that not all PCB manufacturers masks silkscreen with solder mask so if I have pin 1 marked with line going through pin I should expect that from some of them I will get PCB with paint on my pads. Based on it I’m not sure if manufacturers masks copper with drills.
I fill no comfortable with it as having in mind that drills positioning has a finite precision (I assume about the annular required) I imagine a moon-like copper can be left on the board.
I come to work at Saturday just to ask developers (as bug report): Why not allow the drill size being bigger then pad size?
). They want to know what you really want, a plated hole, non-plated or semi-plated (castellation, which may be impossible with a small hole). If you want to leave clearance between the NTPH and copper you should rather make it so.