How to indicate net trace width on the schematic?

Schematic
#1

Hi, I’m new to KiCad, coming from the EagleCad 5 world.

I can’t figure out how to attach a trace width attribute to a net. I tried searching for “trace width” and “attribute” but couldn’t find anything. I tried double clicking on the trace but nothing happened. I’m used to putting trace width indicators on the schematic so the PCB knows what traces need to be wide for carrying power.

Thanks for any assistance,
Lloyd

#2

It is not yet possible to annotate schematics with PCB design rules in KiCad. What you probably want to do is set up net classes for certain nets and assign those a certain width, but you do that in the PCB side (at least in KiCad 5)

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#3

Ok, at least I’m glad to hear that I didn’t miss it, it’s just not there.
Thanks,
Lloyd

#4

Netlist labels in Eeschema get transferred to the Nets in Pcbnew, and Pcbnew has sorting abilities to assign groups of nets to a netclass. So you can use the net labels as an intermediate step.

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#5

What you could do is give such traces a specific prefix or suffix like _HIPWR or something like that. Then you can filter all nets with such labels on the PCB side and assign appropriate netclasses.

Of course it’s likely that you have high power traces and low power traces on the same net, so either you could use net ties there to split the nets, or just set the trace width manually when drawing them.

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#6

Thanks, good suggestion.

#7

Note that in the upcoming Version 6, you can assign netclasses in the schematic (but still cannot show them visually as labels like in some other EDA tools – that part got passed over for V6 but I still think we will consider for a future version)

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#8

To be honest I find it easiest not to bother setting up multiple net classes and instead just set trace widths manually during routing. Net ties are a pain and I only use them when I want to keep a trace separate from a plane on the same net and layer to control current paths.

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#9

Net attributes annotation direct on Eeschema still on whishlit

It depends of some discussion and new graphical object, possible file format change. Because v5.99 is on feature freeze for v6, this feature will be not present on stable version.

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#10

I’d just attach a text comment to the specific schematic net specifying PC trace cross-section area (NOTE: not width, as copper thickness plays a role).
Then it’s up to the PCB layouter to find the best solution, eg, track width, double-sided tracks with or without stitching…

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