Dear All.
I design KIcad layout and i use Via.
Like this…Via pad is so small…
I think that Hole is 0.3mm, but pad is not 0.6mm…
If i want to design new via, Can i expand Via pad??
i want to make Pad 0.6mm…
How to change Via pad or design?
Thanks~
To me it looks like you are trying to use a via for some other purpose than what it’s intended for. It’s meant for electrical connection between layers. In your screenshot you seem to want a larger bare copper ring. Why? Exposed copper is not usually needed for via.
I agree with eelik here. If you want to use the hole to solder a wire in, there are much better solutions with single hole footprints.
Via’s are not really fit to solder stuff in because they have no exposed copper because they are burried under solder mask.
If you want to make big via’s then first:
Pcbnew / File / Board Setup / Design Rules / Tracks & Via’s and then add a few via sizes in the “Pre-defined track and via dimensions”
After that you can select these sizes in the drop down menu at the top of Pcbnew:
I absolutely agree. Do not use vias for anything else than, well, vias. In fabrication vias are treated differently than component or test pads. For example, IPC specifies a large negative tolerance on the hole diameter. The fabricator can and will reduce the diameter. If you then want to stick a wire in it… Solder mask for via’s also has its own rules. Depending on the via protection specified, you might end up with solder mask on the copper.
Thanks.
i know that i can change via size…but my question is that can i change via pad.
i change via size (1mm size, 0.5mm hole). But it is not changed pad…i am curious.
if i want to expand via pad size, it is not possible?
A via has two key parameters
You can increase the SIZE to increase the annular ring of the via (handy for larger traces, drill hit, aspect ratio considerations). However, fundamentally it is a VIA and thus there is resist over the majority (and totally covered if you request tented). If by pad you are referring to exposed plated copper of the annular ring you can place a mask shape over the via (I add circular testpads to make test-vias), but you really should be using a dedicate hole not abusing a via (which is a plated hole but implies certain processes )
In my understanding there is no such thing like ‘via pad’.
Pad for me means a part of copper not covered by solder mask while vias are typically whole covered by solder mask. 3D viewer tries to show it. At via edge solder mask is thinner so a copper is little more visible so you have a little yellow ring at your 3D. If you increase via size nothing will change as solder mask will be looking the same.
That’s my understanding, too. I repeat my first question, “why”, which you didn’t answer. If you need a through hole pad, create a footprint or use an existing one from the KiCad libraries. There are footprints for example for mounting holes and for soldering wires.
So this is what I mean by a "test via). There is 3 via’s just below U23 and one of them I have placed a circular mask to expose more copper
KiCad today (V6 and earlier) does not support custom via padstacks (for example, with one side exposed by soldermask and the other side covered, or one side with a larger pad). This limitation will be fixed in a future version (currently planned for V7) but for now, if you want these kinds of vias, you need to create them as footprint pads instead. We understand there is a use case for this kind of via, we just don’t support it yet.
oh~
Thanks Good information
yes right…
if i need, i made Test pad…
Thanks~
This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.
