The RHLGA 3.76 x 2.95 x 1.0 mm package requires a hole in with clearance and then copper for the microphone.
Clearance around the hole is clearly needed to avoid solder getting in the way of the microphone.
The PAD is needed to isolate the sound channel from the surroundings.
I have tried several methods, but I can’t get the copper clearance around the whole.
In the image below you can see a copy of the 3D model of what I achieved. Further below is a link to the footprint as it is now. There is also a link to the specification of the microphone if needed (some extracts are in the paste image).
I’ve also tried a copper circle with a rectangular SMD PAD on it, but then I can not route it.
However, pay attention to the bzr revision which you need to use. In this instance I would say use an SMD pad with a custom shape; be sure the pad itself, which is your electrical connection point, is part of the copper circle. A normal NPTH can be placed in the center of the circle.
With the “stable” version or a development version without the custom pad shape patch, you can still get this pattern via:
an SMD pad which will be part of the copper circle
2x nested polygons to represent zones to define the circle (this must be generated by a script - kicad has no suitable tools for it)
NPTH
The great disadvantage in this case is that the circular copper cannot possibly be part of the footprint since a footprint may not define copper zones. Using the patched developer version is the best solution at this point, but it ties you to a very specific revision (and all its bugs) until such a time that the custom pad work is merged with the main branch.
Worst case (didn’t test to put it into a layout) you have to switch DRC off when you connect pad #6 (all 4 of them).
But once you got that it should resemble the standard copper fill mode with thermal spokes to the pads.
Do you know how that custom pad shape version does the paste pads?
With a hole/no copper area in the center the pad mask would need to be able to create spokes for the center cover to hold in place for the paste… I’m sure whoever did it took care of it though.
I have tried the new footprint and the issue still is that I can not place a track from GND to the PAD.
Your comment regarding the courtyard & silkscreen is also taken - I had been looking for good guidelines about this but I had not found them.
Now I found this in the KiCAD guidelines:
6.5. Silkscreen is not superposed to pads, its outline is completely visible after board assembly, uses 0.15mm line width and provides a reference mark for pin 1. (IPC-7351)
6.6. Courtyard line has a width 0.05mm. This line is placed so that its clearance is measured from its center to the edges of pads and body, and its position is rounded on a grid of 0.05mm.
6.7. Courtyard clearance is 0.25mm except for components smaller than 0603 at 0.15mm, connectors, SMD canned capacitors and crystals at 0.5mm and BGA at 1.0mm. (IPC-7251, IPC-7351B)
Your suggestion is 3.4x4.2 which ads 0.35 in width and 0.34 in height to the worst case sizes given in the specification: 3.050x3.860.
Apparently you selected the courtyard based on the typical size (rounding these numbers downwards).
I think that the courtyard should be 3.6x4.4mm. Would you agree with that or should we stick to the average sizes?
Hi
I’ve tried several other things and I finaly discovered that I can track to the copper, but not to the pad.
I looked into the code on compiling for windows, but it is a lot of overhead to set it up.
All contributions were usefull ;-). I think the removal of some pads from the solution submitted by Sparky was necessary and made the solution with the soldering paste clear. The first post made me try again with a single pad.
Here is my final result where you can see a trace to the copper:
The housing outline I draw on the fabrication layer to have a reference that I could use for documentation purposes and also during layout (besides the courtyard).
I stick to average/typical sizes for this.
I usually put down silkscreen for outline purposes of the device. In case of LGA/BGA I draw it just outside of the housing outline. More experienced people would not let it come UNDER the device anywhere as I did there as for real tiny stuff the thickness of the silkscreen would become problematic (I don’t deal in those sizes).
Then there needs to be a pin 1 marker of sorts. I stick with lines as I had fabs (Chinese) that didn’t do circular elements which means no marker after the boards came back
I have one on fab (for documenting) and one on silkscreen layer (for placement/assembly check).
The courtyard layer is a rule of thumb thing and for smaller devices I go with ~0.2 mm further out than the housing/pads.
As for which size (min/avg/max) you follow - really up to you I think.
Or do you know an IPC that does deal with this?
My background is hobbyist/small volume that currently does manual assembly - your mileage and needs may vary.
PS: do you mind uploading your final version so I can have a look - in case I can learn something?
The solder paste mask works the same as for all other types of pad - it is simply an aperture which is slightly smaller than the copper land. Breaking up a pad to ensure that there is no deleterious excess of solder, or in this case controlling solder paste amount and breaking up a pad to provide mechanical support for a paste stencil, is left entirely up to the fabricator.
IPC-7251 provides guidelines, but in reality those guidelines are ignored and manufacturers recommend a much smaller courtyard. If the 7521 guidelines were followed, mobile phones might be the size of laptops.
That’s right - no spokes. Even for “Exposed Pads” with thermal vias I create the paste pattern by putting in numerous SMD pads and removing the copper layers to leave only the smaller paste aperture. The large EP itself would have the “paste layer” deactivated so that I don’t get a huge hole in the mask. It’s a great nuisance, but fortunately most components don’t require this special treatment.
I haven’t changed much for the moment, I just changed the angles of the solder paste (after computing the start position using another drawing tool, and there are a few pads less.
I’ll post the fhe final version later:
Before seing this, I’ve aseked the “fabricator” about the spacing I should put between these solder paste areas.
If not in his reply, I’ll ask if they do indeed add these spokes themselves or not.
If they do, there is no need to split the solder paste in the footprint.
Good tip about the lines in stead of circles too ;-).
I’ve read the IPC and I’ld say the question about margins (smallest/average/biggest) is not very clear.
For instance the ADS1115 page 38. Is the Solder Mask clearance included in the upper picture or not? What is the pad width that I should put in the footprint, etc.
The stencil mask is 0.05 smaller than the PADs in each direction, but the solder mask clearance is 0.1 in each direction.
True, but given the millions of products they build, they can violate default guidelines as they work closely with the manufacturer in order to make sure about manufacturability.
Further, in order to miniaturize, they also put several chips together in a single package.
If you look at the Raspberry Pi and similar boards, you can see that there are almost no components external to the main ICs.
For the moment I got as reply that the distance between solderpaste zones has to be at least 0.150mm. I’ve asked about the automatic addition of the spokes now.
The board manufacturer confirmed that they add the “spokes”.
I have to adjust the footprint which I will do in the coming days when I rework the board design.
Pins 2, 3, and 6 should be connected with a ground pour (zone) not thin traces. The whole point of connecting to each of the 3 pins to ground is for EMI (electromagnetic interference). I have personally used this MIC and found it only makes a subtle difference down at the noise floor and how close this is to a switching converter. If you do not care, only one of the 3 pins needs to be connected to ground and you can use a NPTH for the acoustic passage.
With respect to the courtyard, etc, I have found an excellent document on PCB design.
It discusses almost everything about designing a PCB. It is truly a great ressource.
It turns out that the KiCAD recommended margins are the nominal margins for general purpose. You can apply less margin for miniaturisation or more margin for ruggedness.
Thanks, @le_top . but the “almost everything” in your text reminds me that I never finished it…!
(smile)
You linked directly to a document, but the website is HERE: http://www.frontdoor.biz/HowToPCB/
The article you reference is written by the owner of PCBLibraries. He is also one of the most active members of the IPC committees on library related standards, and created the FREE IPC Land Pattern Calculator HERE: http://www.ipc.org/ContentPage.aspx?pageid=PCB-Tools-and-Calculators
The free one is a wizard that will give you the dimensions of a proper footprint based on whatever component dimensions you enter. You can then use that info to create something in KiCAD
The licensed version will actually create the KiCAD files for you.
