I have done 0.8mm devices on 8-layer HDI boards, but have not gone to 0.4mm yet. However, there are may of the same challenges.
A: How to design & layout a 0.4mm BGA footprint “right”? Is my way the right way?
As was mentioned, identify the board house that will be making the board and read their design guidelines. Also, find any application notes that you IC vendor may have. For instistance, Intel/Altera has a board design guidline App Note that cover 0.4mm BGA land pad, via, and escape routing on a 4-layer board:
Board Design Guidelines for Intel Programmable Device Packages
Note pages 14, 18, 27-29
B: How do I specify a VIA as a “Via-in-Pad (Filled & Capped Vias)” in KiCad?
I would add the vias in the pad in the PCBnew layout and not in part footprint, as not all pad will need vias. You will then have to communicate to the board house in extra fabrication instructions that something like
“Uxx, Uxx, Uxx contain vias-in-pads that shall be filled and capped”
C: How to define them in the GERBER files?
Per above, this should be done through the fabrication instructions, as Gerbers alone cannot communicate all the build requirements on complex boards. Make sure to verify that the board vendor confirmed reading the fabrication instructions.
D: Is there any other possibility to layout the inner pads of the package to the outside?
Check out he escape routing in the Design Guide link. At 0.4mm it does look like dog bones are out and via-in-pad is the way to go. Read the docs, follow your vendors guidelines and communicate clearly with the board house and you should be good-to-go. Don’t be afraid to ask the board house questions and let them review the board package before ordering.