It is said it is good practice to connect unused pins to the GND.
But when I connected them , ERC check will report warnings.
So How to do it ?
My GPIO Pins are set to tri-state.
Thank you!
Some microcontrollers I have worked with suggest that it’s good practice to connect unused pins THROUGH A RESISTOR to either power or ground, especially if the pin may be an input at any time during the chip’s power-up or initialization process. My intuition says it is unwise to connect a pin to ground if it may become an output at some time.
Dale
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You mean mcu? It is nrf51822
Thank you. It is a solution
When dealing with a digital or logic device (such as a microcontroller) there is probably no universally applicable, one-solution-fits-all-cases, practice for unused I/O pins.
In general, a floating input pin doesn’t simply have an unspecified logic state, the pin may actually have a voltage that causes excess current to be drawn by the input stage, or possibly cause the input to become an oscillator - either situation may damage the IC. (The voltage on the pin may be the result of random static charge accumulated on the input capacitance, or leakage currents across the surface of a circuit board, or rectified RF energy collected by the unterminated pin acting as an antenna.) Manufacturers’ data sheets sometimes suggest practices such as "Unused pins should be configured as inputs with internal pullups enabled . . . ". (See, for example, https://devzone.nordicsemi.com/question/4130/nrf81522-unused-io-pins/ ) These techniques may work well after the chip has achieved its operational state, but they ignore those first few microseconds after power-up, before the CPU clock has started, before the pin’s data direction can be defined, and before the internal pullups can be enabled.
You certainly don’t want to directly tie an output to ground if there’s any chance that it can ever be driven HIGH (or tie it to supply voltage if it could ever be driven LOW) - even by faulty code. A floating output pin is usually not likely to cause chip damage unless it’s an unclamped open-drain driver, in which case stray voltages or accumulated charge may exceed the output transistor’s breakdown voltage. I have heard stories of EMI transients being traced to high dV/dt on outputs with inadequate loading.
There’s a rather extensive discussion of the design factors at http://www.piclist.com/techref/logic/xtrapins.htm And yeah, a lot of engineering design comes down to evaluating the tradeoffs of various alternatives in a particular situation.
Dale
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Great explanation ! Thank you !
Most often the advice for GPIO is:
–Make output and drive high or low; or
–Make input and use internal pull-up
Tieing hard to ground is not recommended
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Mostly only a problem on low low current designs.
But define your gpio as outputs and let them float.
Pure inputs can be bolted GND on modern chips.
Pull up / down just adds to the bill of material and board space.
There are exceptions of course, but rare.
I think it’s all been said already, but here is my 2c.
Some MCUs and SOCs have dedicated inputs, which can and should (if not used) be tied low, for things like TEST, ERASE etc. These are generally used during development, but you really don’t want ERASE accidentally going high in a production unit.
To be flexible for development/production, they could be connected to ground via a zero Ohm resistor. If the pins might be
For logic gates, connect inputs to something high or low, but don’t leave them floating. This maybe where the lore about tying pins low comes from.
But any bidirectional pin (any chip), should never be tied directly to ground (or +V), and there is rarely a reason to do so.
It’s always worth examining challenging folklore to see if it still makes sense, often it is either corrupted through retelling or no longer relevant.
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Read what the chip maker says to do - Google is your friend here.
Most microcontrollers have multi-purpose GPIO. These often default to inputs. Leaving these floating can cause high supply currents to flow.
Bidirectional pins should not be left undefined, modern cmos IC structures can reach 50mA per gate leakage if the pin sits at a logic half.