I have SGND zone on layer 2 and a GND zone on layer 3. The chip, MAX17633, has pin 21 on the back of the chip and that connects to SGND. I did that with 4x4 array of vias that connect to the SGND layer.
How can I also connect these vias directly to the GND plane on a different layer? I looked at using a NetTie, but Tech Support at Analog Devices recommended to connect the 16 vias to both layers. That is how they designed their evaluation board.
This is the MAX17633 footprint.
Each of your vias connect to only one layer. I just want the SGND via to connect to GND as well. I donât have space to have both a GND via and a SGND via.
If I just connect the SGND net and GND net to pin 21, I get pretty much what I want. Except, now all the GND vias in other locations on the board are also tied to SGND, which I do not want. I want to keep SGND and GND separate except for one place, that is pin 21 under the chip.
Normally via canât connect two nets as track canât do it.
You should have all zones under IC being the same net as pad 21.
How to make SGND island on GND zone and then connect it wholly around it with GND I donât know.
But using 4 user defined net-ties (one for each island edge) it probably should be possible.
Canât be sure as I have never used net-tie.
I wonât suggest my way is the one for your process - My goal was to show connections to Vias on different layers. Connecting NET, Traces, PADs, Zones is a learning process that involves starting out in a Simple manner then, expanding to encompass the needed design aspects.
Thereâs also a logical order of sequences and Part Items (Vias, THT, Zones, FillsâŚetc) that help to make the desired âElectricalâ connections.
Net-ties have a Cylindrical barrel connected to All Layers thus, need only connect to desired traces/etc. DRC settings are importantâŚ
Below, I show connecting Four Layers to a THT. Look at the 3D-View⌠Result looks identical to Viaâs but is easier to work with. And, you can edit the settings as neededâŚ
ADDED: Before someone posts the VCC/GNDâs are all connected, I know that⌠A correct circuit isnât the point of my postâŚ
What is a THT? I donât have that part in my parts library.
THT is " Through Hole Technology" and it refers to components that pass through the PCB as opposed to SMT âSurface Mount Technologyâ that sits on the top layer, so for connecting layers THT might be able to help. 
when I saw your remark for asking the meaning of THT, my eyebrows started getting darker, but I did not respond. I guess we all have our muddy thoughts every now and then.
Another part that confused my is the title of this thread. Normal viaâs go through the whole PCB, and therefore always connect to all layers, which have copper of the same net. When reading your post again (and again (big eyebrow time)) It dawned that you actually want to use the via itself as a net tie (That is a standard time, look it up Edit: you already did).
I have not checked, but maybe it works if you define a new footprint, and use THT pads as a net tie.
Another method, for which I am sure it works is if you create zones on each layer with the same net (so your viaâs connect to all those layers), and ten use a net tie on each layer to split off the net to some other net. I do not know why you write you do not want to use a NetTie. This is exactly what NetTies are for. You can design them in any shape, so physically the copper looks like itâs one piece, but it has to be defined in such a form that KiCad can distinguish between the two nets. NetTies have changed a bit in KiCad V8, and I have not experimented with them yet, so no further details.
Simple solution⌠Set both Ground-Layers to the same Name. The Max wonât know anything about it
Image below shows Buried Blind Vias. The Vias on Left touch this Maxâs Heat-Sink/layer. Donât know if thatâs a goal of yoursâŚ
4-Layer Board, Two inner Layers with Filled Zones (GND & SGND). Top/Btm Layer Hidden, No Net-Ties. No FussâŚ
I cleaned up/deleted some of my PostsâŚ
@paulvdh Thank you for joining the conversation. I always learn something from you.
I have been working with the tech support engineers at Analog Devices on the layout of my board, which uses 3 MAX17633s and a MAX17320 BMS . I have been using their MAX17633 Eval Board as a guide, as it works. They recommend using the vias connected to pin 21 (the bottom of the chip) as the place to tie SGND and GND (they use PGND) together in one place, and not the NetTies as I originally used.
I suggested using the vias you have for the exposed pad ground as the âstitching viasâ between SGND and PGND, forgoing the net ties. Check out the EV kit layout (pics below): the vias in the exposed pad are directly connected to the main copper pour on each layer (except the top layer, which has the exposed pad direct connected to the vias so it doesnât show). Furthermore, there is actually no other point on the board where PGND and SGND are connected, except for through these vias (and ignoring the GND test points). This is the best layout practice, as it 1) ensures return currents are localized to the chip, reducing noise, and 2) Allows all that copper from the pours on different layers to share the duty of carrying those high currents.
clips from the different layers on the MAX17633 Eval Board
Of course, I know what THT means. I was confused by the use of the term to denote a particular footprint.
I tried building a custom THT footprint âPhredâ with two pins, 1 and 2, one top of the other. I then placed it on the board as a test and connected pin 1 to SGND and pin 2 to GND (GND = blue layer 3, SGND = green layer 2). It does not appear to be attached to either layer. I also set each pin with a Pad Connection of Solid and Fabrication Property as Heatsink pad
Maybe they are connected properly and KiCad version 7 does not show it properly?
I also tried to run a track from a via connected to SGND to Phred pin 1 and it wonât connect. Same with GND and pin 2.
A further requirement is JLCPCB only offers TH vias and no buried or blind vias on a 4 layer board.
I am still unsure on how to connect pin 21 and only pin 21 of the three MAX17633 chips to both GND and SGND zones on different layers.
To avoid confusion, get your terminology right. The for yellow circles with the black holes on the top are pads and the white circles with yellow center are viaâs. They look very similar on the PCB (Except for the mask and paste layers), but they behave differently in KiCad.
Hereâs the Answer.⌠(sorry, you didnât pickup on what I posted). This should Clarify itâŚ
This Stock Part (similar to Max) has:
⢠SMD Contacts for the CHIP
⢠F_Cu Heat-sink Pads
⢠B_Cu Heat-sink Pads
⢠Unburied VIAs (i.e., Standard Vias)
The MAXâs VIAs are for Removing Heat from CHIP
You do NOT need to add any extra VIAs unless your MAX doesnât have the Vias/Heatsink Pads
⢠First, Create the Two Zones (SGND and GND)
⢠Now, place the MAX on top of the ZONES. The MAXâs Vias will be in Contact with these Zones.
What you Donât Want To Do is Fill or Refill the ZONEs after placing the MAX on the PCB. There are settings for Default Auto-Refill, turn it Off.
Thus, If you Fill/Refill the Zones, the VIA connections to these two Zones will be lost.
Example using Stock Part: HTSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x5.4mm_ThermalVias
Shows the Zone(Heatsink Pad) on Bottom of the Part and SMD Pad and VIAâs
Shows Side-View - you can see the Two Zones I created, the Partâs Vias, in contact with the Zones. The Zone and or Vias can have Net assignments.
I repeat: What you Donât Want To Do is Fill or Refill the ZONEs after placing the MAX on the PCB.
This is what you should see (no Black Space around the ViasâŚ)
If you Refill the Zones, this is what youâll get (see the Black Space around Vias)
If re-calculating internal zone geometry (with the b key) âdamagesâ your project, then itâs a very ugly method.
But the other methods also have their drawbacks. A THT pad used as a via still connects to only one net, so this means you have to place net ties elsewhere. At the moment, the implementation of net ties relies on pads, and SMT pads on inner layers are also still difficult in KiCad.
A method that may work is to draw a graphical rectangle around the THT pads used as viaâs. KiCad does not modify graphical items to create clearances.
And of course, the whole problem can be avoided if all items are just part of the same net. I am not sure why you are splitting the GND nets in the first place. Mostly this is an old and deprecated practice. Although it is a stubborn misconception that this is âbetterâ in some perceived way. When you merge all the GND nets into a single big net, you do have to manage how currents flow through the GND plane. Itâs not a simple âwhereverâ it fits. Donât put a sensitive analog part right next to a very noisy SMPS circuit. All signal content follows the âpath of least impedanceâ. For DC, this is the ohmic resistance, but starting from a few kHz signal content, impedance is dominated by loop area.
There are 4 Hot-Keys for the Zones but, All will remove connections.
However, Prefâs has a setting to turn On/OFF Auto-Filling.
And, the various Plot panels have a Checkbox to âNotâ Check the Zones (Checking, as I Recall, causing Re-FillingâŚ)
Tip: If the Zones got Refilled (âdamageâ as paulvdh mentions), you can Drag the Zones away to a blank area then, refill them. Then, Drag them back and Donât RefillâŚ
Still the same. Itâs a horrible kludge. At the very worst, you re-generate zone geometry just before creating Gerbers, and you send faulty data to your fab. That is something you should stay far away from. I just donât see that method as a viable option at all.
Simple and Clean (of course, that depends on the project/PCBâŚ)
I agree 100% with @paulvdh .
It seems the default for Auto Refill Zones is Off. At least it is in my KiCad version 7.0.11. Probably to make the program faster.
Creating Gerbers should be âautomaticâ at the end of the design and not depend on remembering how to manage different kludges built into the design. IMO, greater than 90% chance of paying for a DOA board with this design strategy.
Also, every time the Design Rule Checker is run, it automatically refills all the zones, and it has to do that to, well, check the design. With @BlackCoffee suggestions the Design Rule Checker will not be able to do its job, so another potential for a DOA board.
Not worth the risk of a DOA board.
This thread is getting quite long now, and still a bunch of things are not clear to me.
Take for example this part:
Why do you think that GND is not connected to all those THT pins? They look perfectly well connected to me.
Another part I donât understand is:
and in extension to that, your whole idea of splitting the GND net into different sections. I do not know to which extend you:
but even seasoned engineers sometimes keep on repeating 30 year old paradigms instead of learning new things. A very good and informative video is the 2 hour long talk from Rick Hartley on Youtube. And really, those two hours are worth watching. Preferably even compounded with videoâs that show FEM analyses of currents and how they behave. For example from Robert Feranec. I am also at my limit here. I also do not know enough about your design to give further recommendations.
Seriously, Every program has shortcomings per Userâs personal likes/dislikes. I Hate Kicadâs File Mgmt system and having to make certain settings in different panels but, otherâs like it as-is.
You asked How to do it in Kicad, I showed how⌠I didnât Write the Code/app⌠Post a Feature Request to KicadâŚ
Sometimes when I get on my Harley and rotate the Throttle, I want the bike to go down the road but, somehow Harley wantâs me to put it in gear and use the clutch⌠Kludgy Bike!
Strange analogy 
Perhaps TOO much coffee. However I think this seperate ground stuff has had its day and careful thought about your design and current flow combined with well thought out copper pours is the way to go, however this thread has definitely run aground.
