The layout guidelines for TI’s BQ25895 battery charger IC recommends routing analogue and digital grounds separately, joined at a single point on the device’s thermal pad.
TI’s reference design shows separate full-board analogue and digital ground plane layers connected together by the footprint’s thermal vias.
I’m worried about power dissipation, and copying their approach would allow both GND plane layers to be used for thermal dissipation.
Understandably, KiCad doesn’t want to join separate nets in this way, so I’m left with connections to only one plane layer, (to be honest, I’d disappointed if it made this easy).
forget about the concept of an analogue ground and digital ground and instead concentrate on placement of analogue and digital components such that their signals (and return currents) don’t cross.
use net-ties to create a link and physically place this by this chip and then use zones under the part filled with via’s
After reading my original post I can now see that its not clear I was trying to achieve a way to link two separate, full board area plane layers, with different nets, using the component’s thermal vias. I have edited my original post to clarify this.
I’ve previously used net-ties when splitting a single plane into analogue & digital zones, so this was my starting point when joining these two plane layers together. Unfortunately, a single via will only connect to one or the other planes, so the best I could achieve is splitting the thermal pad into two separate zones with half connected to one plane, and half to the other. I’d get much better thermal transfer If I could get each via to connect to both layers.
I could use a Gerber editor to ‘fix’ the problem, but that’s a nasty solution, and likely to cause problems down the line.
@Naib, I think your first suggestion is probably the way to deal with this; unfortunately, the component pinout doesn’t help here, but I’ll do the best that I can.
Well, looking at the part I think it is doable but it just takes some care during layout. Its a switcher so you always have to be conscious of the layout and routing.
Power ground connection for high-current power converter node.
Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to
ground connection of input and output capacitors of the charger. A single point connection is recommended
between power PGND and the analog GND near the IC PGND pin.
Exposed pad beneath the IC for heat dissipation. Always solder PowerPAD Pad to the board, and have vias on
the PowerPAD plane star-connecting to PGND and ground plane for high-current power converter.
with no dedicated “GND” for the digital interface, layout is key to ensure the switching noise does not go near the digital. Luckily the chip looks ok for this. The top and right sides are for the switching and thus the return path for the output decoupling is key. The output inductance and initial output cap should all be in the top-left corner area and surface tracks to close the PGND connection back to the pins 17 and 18 (not via’s to the GND plane). This means the caps need to be near these pins. The circulating switching current will therefore return back to the internal switcher with the smallest loop.
The exposed pad can then be tied to GND for thermal, reference and digital return current needs.