How to combine schematic symbol pins for footprint with more pins

I am drawing a schematic where I am using a MOSFET, but the footprint is a SOT-8 package. What is the correct way in KiCad to combine 4 pins in the footprint to 1 in your schematic?

One way of doing it is called “pin stacking” in KiCad.

The idea is to have one visible pin in the schematic, and put more invisible pins in the same location in the schematic symbol. Pin stacking is very common in KiCad’s default libraries.

The latest KiCad versions have an (annoying) curiosity that default library symbols can’t be directly edited. So, to get an example, first place an ATMEGA328 in your schematic, then select it and press [Ctrl + e] to edit that copy in the Symbol Editor.

In the screenshot below you can see pin 4 (which is the normally visible Vcc pin), but also some cyan text, which is an invisible pin.

If I move pin 4 aside a bit, you see the other pin better:

Ah, indeed, the pin type of those other pins is usually set to Passive, to prevent ERC violations.

Also:
Pins in schematic symbols should always be on a “50” grid. This makes stacking pins easy. KiCad depends on exact alignment for recognizing connections. More guidelines for creating schematic symbols in the KLC (KiCad Library Convention)

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“correct” is a tricky word. It may depend upon who you work for and how the boards will be built. This footprint fits MOSFETs in either SOT23 or SOT-6. The SOT-6 package gets rotated 90 degrees (compared to the SOT-23) on assembly. For this, I think it would be confusing for the schematic to show anything more than 3 pins. The key would be the assembly drawing.

Footprint pin 3 gets the MOSFET drain. It has a large area which is good for power dissipation.

BTW I do not remember seeing MOSFETs in 8 pin SOT, but I place SO-8 MOSFETs similarly on a different 3 pin footprint.

Arguments are welcome.

image

This is what I do.
I don’t know if it is correct or not, but it works for me.
I started with a Kicad library 3 pin NMOS, put it in a rectangle, placed some pins around, and a few graphic lines. Note the gate pin position to avoid a wire crossover.
Under 10 minutes work and doesn’t take up too much real estate on a schematic.

ksnip_20220329-180307

And maybe a SOT-6

ksnip_20220329-182519

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