How to check for Soldermask/Track spacing

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Hi all, JLCPCB just rejected a flex design I uploaded because of a coverlay-to-track clearance violation (coverlay seems equivalent to solder mask). Rule is this:

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image1357×199 27 KB

See also PCB Manufacturing & Assembly Capabilities - JLCPCB

I wonder how I could set up clearance rules so DRC shows the violation. So far no idea.

I thought of loading both gerber files (copper and solder mask) into the gerber viewer and let it check for clearance. Unfortunately the gerber viewer can’t do clearance checks.

Thanks - Martin