How to calculate Differential Pair widths/spaces (for ethernet)


#1

Hello Community,

iam currently designing a board that contains an 100MBit Ethernet connection.
and thats the first time iam doing ethernet things.
so i have had a look at a App-Note of the PHY chip:
http://ww1.microchip.com/downloads/en/AppNotes/en562748.pdf
it contains a lot of good information -
and for me its clear i have to do a differential pair for the TX+/TX- and RX+/RX- traces.
i know that i can use the differential pair rooting tool.
i also know that i have to do a 50Ohm impedance per trace -
so i opend the KiCad PCB Calculator and tried to get some values out of this
as input parameters i looked up the material datasheet from my board house and got:
Er 4.6
TanD 0,015
my board thickness is 1,5mm (base material)
and 35um Cu

and anded up with:


so width: 0,47mm
spacing: 0,15mm
the trace width seams really heavy to me.
i have also tried it with this calculator:
http://www.eeweb.com/toolbox/edge-coupled-microstrip-impedance/

but there it came to 0,7mm width traces.

i have found a document that says:
width 0,25mm
separation: 0,25mm
separation between RX-pair and TX-pair: 0,5mm (or gnd)

currently my trace will be about 35mm long.
(and additionally i have to add some ESD things so they will get slightly longer)

one question that came to my mind is - how much clearance should i leave around the trace pair? (to the next pair and to the ground plane.

is here somebody that has some experience and is can share some tips?

iam open to every bit of information to understand better what is relevant and how to do it correct :slight_smile:

sunny greetings
stefan


#2

I make that clearance at least 3 times the distance from your diffpair to its reference plane (i.e. 3 * 1.5 mm = 4.5 mm). It’s sufficient to minimize your diffpair coupling to unrelated copper.

By the way, I’d recommend using Saturn PCB Design Toolkit for impedance and other PCB calculations.


#3

Ethernet is a balanced transmission line system, ~110 Ohm impedance. Focus on that, not the 50 Ohm of individual traces.
Long parallel runs require the pair twist to be crossed over to balance crosstalk


#4

The tracks are wide because it’s 1.5 mm to the ground plane. On a 4 layer, the tracks would be much narrower with a ground plane typically 0.2 mm down. The calculator tools like the one in Kicad are approximate. ATLC (also packaged with a GUI as MDTLC) is very good. It’s just 100 Mb/s Ethernet, so you’ll be fine even if the impedance is off a bit.


#5

If you are looking for a free 2D field solver software, there’s Controlled Impedance PCB Planner (https://github.com/bkuschak/cipcb). It’s based on atlc and mdtlc. I also discovered recently TLineSim (http://www.maartenbaert.be/alterpcb/tlinesim/). It’s very good and fast.
You can have a look on the project AlterPCB on the main page of the author of TLineSim. it’s look like nice.