I have a PCB with an ~80 V DC bus. For safety and creepage I want 0.6 mm clearance for this voltage everywhere on the board, which I have set up using a net class.
However, I have two nets that are both always at the same 80 V potential (they are effectively shorted together functionally, but are separate nets in the schematic for topology reasons). Because there is never a voltage difference between them, I would like the clearance between these two specific nets to be only 0.2 mm, while still keeping 0.6 mm clearance between either of them and any other net.
Right now I assigned both nets to an âHVâ net class with 0.6 mm clearance, which works everywhere, but I cannot find a way to locally allow a smaller spacing just between these two nets without lowering the clearance globally for the entire net class.
How can I tell KiCad that these two specific nets are allowed to be closer together (e.g., 0.2 mm), while keeping the rest of the HV net class at 0.6 mm? Should this be done with custom rules, rule areas, or some other mechanism?