I have a problem understanding how to achieve evenly spaced tracks. I know that I can set a minimum clearance in the board setup. Then the interactive router will space the adjacend tracks when I push one of the tracks acordingly. But this works only for very small values. If I set the minimum clearance bigger, then I run into spacing problems, when I want to route between through hole pins.
Let’s say, I want to space a bundle of tracks in a specific area with distance of 1in. What I’m doing currently, is using shortcut N and shift+N to change the grid space forth and back constantly. Then, for example, the tracks are not on the grid exactly, but 0.5in offset. Then I have to set the grid to 0.5in and then count two raster points down.
For horizontal and vertical tracks is this relatively easy. And also with this coarse values. For 45° tracks, it’s already not so obvious anymore. And with smaller values, I’m never sure with the 45° tracks, if they are evenly spaced or not.
Now is my question. Is this the way to do it, or am I completely wrong and there are much comfortabler or eleganter ways to achieve this?
Thanks for your reply. It is not strictly required by my application. I meant it just as an example with easy to hanle numbers. Spacing can also be smaller. The question is meant generally, how to achieve constant spacing between tracks.
I don’t want to go to much off topic. Background story is this. I design a PCB for my father. He is a retired electronic ingnieur and is constructing a little project. Project is a solarpanel, which adjust itself over two axis so that it is constantly facing in an optimal angle to the sun. So, I have the knowledge with CAD design, but I have only basic knowledge of electronics. My father has the knowledge of electronics, but not specifically regarding PCB design. Then the topic came up about EMI and that this could lead to issues. Therefore we have increased a bit the distance of the tracks.
I think EMI should not really be a problem. Because, this is already a second revision of our board and the first one worked well already.
I agree with that. if it’s just for a solar panel, then it’s just DC current, and EMI is not an issue at all. There could be an issue if there is an MPPT between the solar panel and an battery (or other gadget), but the simplest solution is to filter the thing so it does not feed back AC ripple to the panel.
Also, Solar trackers have been done for 40+ years, and usually they do not come to much. The added complexity of rotating the panel, strong enough to resist wind forces, and the room needed to prevent multiple panels from being in each other’s shadows make it both expensive and big. combined with the ever lower cost of the solar panels themselves, rotating them just is not worth all the effort.
Maybe you can find some numbers about the extra cost and benefits.
Also, if you align the rotation axis of the panel with the axis of the earth, then you need to turn the panel only around one axis. (amateur) telescopes often use a system like this.
If you are thinking about radiation from your PCB and sensitivity to external disturbances then most important thing is to have continuous GND at one PCB layer to ensure for each signal track the closest to it return path (works good in both directions (radiation/sensitivity)). Even with 2 layer PCB in many ceses it is possible to have continuous GND at one layer. My example:
If it is not possible then it is reasonable to use 4 layer PCB just only to have continuous GND layer.
If you are thinking about interference between your own signals than increasing distances between tracks can be helpful. But it not calls for evenly spacing. You should understand what signals you have in your tracks. If for example you have 3 digital lines driven directly by the IC and one line coming to it. And you know that this one line is driven relatively weakly (like 1k internal resistance) than you should try to make distance between these 3 lines and this one being bigger and you need not to worry about distances between these 3 lines. I had such case with lines filtered at shield border. Inside shield input lines were driven weakly because of filtering and output lines being paralel to them were driven strongly as filtering was still in front of them.
I have seen the information that having clearance between tracks being 3 times track width is almost always enough to avoid interference.
In typical case I have track width 0.25 mm, clearance 0.2mm and grid 0.1mm. So routing according to grid I place tracks with 0.25 mm clearance. If I have a room I route them one grid step farther.
You never need exactly evenly spaced tracks so KiCad is not asked to have such feature.
Many thanks to all who have written.
I think according to information. It should be not a big problem then. I did not mentioned, that my application has a bit more than just motors and drivers. The PCB has also humidity, tempratur sensonsors (not on the same board, but connected to board) and a LoRa module as well, to send actual battery and other data to my LoRaWAN Gateway at home.
I have also attached a few pictures. Hopefully not gone to much off-topic.
Regarding the evenly spacing. Sure it’s not required. I think it’s jst my OCD is triggered, if the track spacings aren’t equal.
p.s. I know, there are many such applications. But I think, this is a unique combination with LoRA and a RS3485 connection. And it’s what my dad have wanted, to develop almost everything alone and by scratch
Spacing between tracks helps when you are trying to minimize interference between them.
It can make emissions and susceptibility worse.
The best way to improve both EMC emissions and EMI protection is a ground plane.
I see ICs there with no decoupling capacitors near them.
Also think about protection against ESD on any exposed I/O.
I have to say, those traces routed that way, looks . . . pretty. I’ve seen TVs and other electronics that look that way. I’m not OCD, to much, but I like it.
I think you could use the push and shove, and walk around routing mode to do this. It is a bit of a hack, since that’s not what the tool was meant for, but does work (to some extent). YOu can adjust the clearence in the net classes editor.
But for what its worth i have wanted a follow this track from here to here with offset of function for ages.
P’n’S “throws” tracks, not only the track under work but the shoved tracks, too, unpredictably. It doesn’t work for this. As I said, I found “walkaround” to be fitting for this task.
p.s. and for center a track between through hole pads?
What I currently do is select two pads and a track and use the distribute horizontally or vertically function.
But one must be careful with this. Because only exactly the selected line from the track is centered then. the track segments before and after are then misaligned and needs to reconnect them properly.
Or does someone know a better way for centering a track between two pads?
In my opinion the simplest way is to select grid to have it exactly in the middle between pads (having pads ‘in grid’). SO cases have a raster of 50 mils. For many years I was working with grid being set to 5 mils. I have never noticed any problem with routing a track exactly in the center between pads.
Thank you Piotr. Okay sure that works when the parts are exactly on the grid.
Think when I have let’s say 10 resistors which I distribute evenly with the distribute option then it could be that the parts aren’t exactly on the grid. or when resistors are mixed with capacitors which have a slightly bigger footprint, the it could be that it isn’t on the grid exactly. Then I guess, I should just not use the option to distribute it and place them manually, to be able to do it like you described then.
I believe you know that it is the initial source of all your problems.
Why not just place footprints manually in grid with equal distance. It will take you less time than later trying to position tracks by positioning one segment and then redrawing the rest of it.
You are not creating 1920x1200 LED display matrix to have too many footprints to position them manually.
I have never used tools to evenly distribute footprints.
Since in 2017 I moved to KiCad I decided that all my footprints have courtyard in 0.1mm raster and I work with 0.1mm raster. If possible I place each footprint touching the previous one. If need some space between them then my space is always integer multiple of 0.1mm.
Edit.
After posting my answer I read your post once more and realized that I wrote the answer not reading your last sentence:
In my opinion it is the best solution if you then insist on routing tracks exactly in the middle between pads. But that tool exists and probably is useful in some cases.
Good morning @Piotr, I fully agree. And it matches exactly, what I intuitively recognized, that just placing parts manually and sticking to the grid will avoid the described issues. It was always naging in my mind, that I’m not sure if I’m doing it right, or if I just misunderstand some of the options and features of KiCAD.
Such confirmation helps a lot, knowing that I’m not doing it conpletely wrong. Have many thankt for your kind help. And also with the additional tipp with the 0.1mm approach. I think, I try this too and adapt it.
I use only my own footprints that in many cases come from copying KiCad footprint and modify it (they not always have courtyard in 0.1mm). I place them touching one to another. KiCad V5 DRC didn’t tested it but in later versions DRC has a warning on it (I switch it off).
I also have silkscreen exactly at these courtyard and DRC probably also have warning about it.
I use courtyard rectangles with ref inside (on the background of gray copper) in my documentation. And second picture - the same but with values instead of refs. Because of this I have also Ref and Value at courtyard layer. These were my first decisions in 2017 before I even designed a first KiCad PCB. I would use another layer for refs and value if there were extra layer pair to be used by user but there aren’t. I don’t use refs or values at PCB (it would need extra time to position them) so not have them at silk. In past (before 2017) we ordered PCBs without silk at all. The reason was less layers in Protel 3 than now I have in KiCad and we used its silk layer for what I now have at courtyard with for example diode cathode identification (to be seen in documentation). What (if printed at PCB) can lead to silk being placed over pads. We could use silk (by sending to manufacturer one of graphic layers as silk) to place manufacturer and PCB id texts but we found printing it at soldermask looking better (you got gold texts).
