I am new to SMD layouts. I do not see how to connect ground (the inner pad) on a T2044-4C package.
I learned from this forum to use a via to connect, say a resistor pad to another layer using a via (3.3V in this example on an inner layer) -
I don’t see how to use this technique to attach the inner ground pad on the T2044-4C package.
Thanks!
You connect such pad to other layers using vias directly at this pad. In KiCad library there are footprints having thermal pad with vias and openings for paste located between vias.
And in your footprint if from any reason you don’t want vias at pad it looks there are enough space at corners to connect there pad to vias being out of it.
Do I need a different footprint? I got the one I am using from DigiKey for this part.
I found an evaluation board for this part the MAX17633, MAX17633 Eval Kit and it has pictures of the pcb layout. The ground plane has a 5x3 array of vias under the GND pad of the MAX17633.
Do I add these by hand to my pcb design? What size and how do I connect them to the GND pad of the part? Is there a less manual way of doing this as with other parts that have a GND connection, then automatically connect to the ground plan when I place them in the design.
Thanks
Kicad treats these as Through Hole Pads that are placed in the footprint using the Footprint Editor.
The footprint offered in the evaluation kit (not the one you mention above) is a TQFN - 20 in either 4 or 5mm package.
This TQFP package is in the Kicad libraries. I’d suggest opening one of these in the Footprint Editor so you can see how they are constructed and how you can modify them.
Below is one example:
Note: I highlighted and moved one pad from the center. You can see the pad properties in the Properties Panel.
@jmk thanks for the clarification and example. The datasheet for the MAX17633 has “package code” as T2044+4C, and package type as 20 pin TQFN.
I edited the footprint and came up with this using your example (diameter 0.5, hole size 0.2, circular, through-hole, Heatsink pad):
Now, the Design Rule Checker does not complain that pad 21 of U701 is not connected to GND!
How does it look? Too many holes? Should the outer gold ring of the pads I added touch the red rings around the chip’s pins? I am not sure what those thin lines represent.
I did not find the TQFN packages in the KCAD libraries I have installed. I am using Kicad -7.0.11.
So, to summarize, the procedure is to edit the footprint and add the pads as I did in this example? Are there any recommendations or rules of thumb for size and number of pads to add?
Should I do this for say a resistor pad connected to ground, or connect a trace to a via to ground next to the resistor pad? Why is one method preferred over the other?
Thanks again!
Lots of questions 
Good!
No
The gold and red lines are the copper to copper clearances for the pads. Find the many clearances in “File > Board Setup > Design Rules > Constraints”
The ring shows the minimum distance allowable, without DRC complaining, that you have set, between the copper pad and the closest copper, be that another pad or a track.
The “rings” can be toggled on and off in “Preferences > PCB Editor > Display Options > Show pad clearance.”
Sorry, I selected a TQFP package by mistake for the above example. I had not bothered checking the dimensions for this reply. I have edited my earlier post for future readers.
Yes, and consult the Data Sheet.
Not good practice. The resistor to pad connection can suffer solder starvation when some of the solder is wicked into the via.
Yes. Solder joint starvation doesn’t occur.
I know one rule. Hole in these pads should be not bigger than 0.3mm. The bigger holes tend to stole the solder paste during reflow soldering.
I am trying to not use too many such pads to allow me at other layer make as short as possible connection between laying at opposite IC sides VCC pins (not around the whole IC but under it). But it is my own invention and I’m not sure if it is the best. I don’t have a problem with power dissipated in my ICs so I can have less number of holes.
The more complicated issue is with paste openings. They should be between holes (taking in account also stencil positioning tolerance) so when spreading the paste it will not be pushed into holes. There are many app-notes describing what percentage of the pad area should the sum of the hole areas be? I have seen numbers from 25% to 80% (I am trying to have 50%). It also strongly depends on thickness of the paste stencil used so agreeing this with your assembling company is a good idea.
My manufacturer questioned one my design saying that paste openings are too close to thermal pad border and when element is placed at PCB (machine does it relatively strong and fast) the paste may be splashed, increasing the risk of short circuiting the thermal pad with one of the other pads.
