Horizontal Connector Pin Header Clipped by Board Edge

Layout
1

Hello,

I’m on my way to designing my very first PCB, which includes a horizontal 3-pin connector. I have the pins intentionally extruding out of the board edge, but the DRC warns me how “silkscreen is clipped by the board edge”. Is there a change I can make to the connector symbol to fix the warnings, or is this configuration not a good idea?

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Connector footprint: PinHeader_1x03_P2.54mm_Horizontal

Also, I’d appreciate general feedback as well!

  • Jeneus
2

You can acknowledge it and then dismiss it and ignore it. Like I do with my wife.

Hardly any my of designs are 100% free of any DRC warnings. DRC Errors on the other hand . . .

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3

You can right click on any of the DRC violations and then exclude it. This is what DaveL meant.

But the silk screen sticking out of the PCB edge can lead to production delays, as it may confuse the PCB manufacturer. I would fix it by:

  1. hover over the footprint.
  2. Press: [Ctrl + e] to load the footprint in the Footprint Editor.
  3. Remove the silkscreen lines.
  4. Reduce the courtyard so it also fits inside the PCB.
  5. Close the Footprint Editor (KiCad prompts you whether to save the changes back into the schematic).

Those steps are enough as a “minimum”. But if you want to do it neatly, then also export the modified footprint to a (project specific) library, and update the footprint link in the schematic so it “officially” uses that modified footprint.

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4

Assuming that such connector will never be used in the middle of PCB I would export it into global library.
My footprints for such connectors have silkscreen only at their ‘pcb part’.

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5

Whether you put such footprints into a project specific or a global library is a personal preference. On itself, the project is “works” even when you don’t put the footprint in a library, but this has two disadvantages:

  1. KiCad complains a bit, because it can’t find the footprint in a library.
  2. There is a risk of loosing the modified footprint during the Update PCB form Schematic [f8] procedure, as it can be replaced by a default footprint.
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