Homemade boards: NPTH connected on one side only

[retiredfeline]

Sorry, maybe I’m thinking too simplistically, but it seems to me you have two kinds of pads.

1. Those for THT components you can solder both sides. In this case let it be a plated hole which isn’t actually plated because you are milling and the lead functions as plating after you solder.

2. Those for THT components you can only solder one side. In this case you need to make modified footprints that have a pad only on one side.

Of course it’ll be a lot of work if you have lots of the second type, more so if they are mixed with the first type for a component.

[UgaBuga]

@retiredfeline

Those for THT components you can only solder one side. In this case you need to make modified footprints that have a pad only on one side.

How do I do #2? I am unable to figure that out. I can’t get holes that connect to a copper layer on only one side. That was my original question.

[retiredfeline]

I don’t know if the footprint editor allows such pads to be created; obviously I’ve never tried. Maybe not as a TH pad but as a SM pad with a separate hole in it?

[UgaBuga]

That’s a clever idea! but I can’t get it to work, because the clearance around the NPTH hole will cover the SMD pad (and for some reason Kicad really wants NPTHs to always be isolated from copper). Now I’m trying to figure out how to change that clearance setting - how do I do that since NPTH have no netclass? I tried setting the default netclass clearance to 0 and that doesn’t seem to affect it. Local overrides will not accept a negative pad clearance.

[retiredfeline]

I wonder if you could create a pad with a copper free hole area in the middle for the drill hole but maybe the system doesn’t allow interior polygons. Ok how about a tiny channel so that it’s still one polygon. But this is getting too weird for me.

[BlackCoffee]

Sometimes ‘my’ confusion arises from the different languages we speak so, I avoid reading too many posted answers and go to the original Question…
"How do I tell Kicad “all through holes are not plated, with a pad only on the back side?”

That said and, for my general need for using Kicad to output Gerbers I can easily use for CNC Milling, this is my approach:

• I Make the PCB layout without fussing or considering adding ‘Filled Zones’ as the PCB stock boards are Filled on one, or two sides.

• I set the Part/footprint Pad for Bottom (and/or Top) layers but, if Milling a Sigle-Sided PCB, I don’t often bother with setting the Top because (for single-sided) it’s only a Graphic in the 3D-viewer. Most of my custom footprints have only one-sided pads (Bottom). But, if using a Stock footprint, I may/may-not bother…

• NPTH un-plated: I usually Draw the Hole (or other shape) on either the Edge-Cut or User layers and Set them as a Contour in my Milling program (CopperCam). Just my preference… but can do it other ways.

• Understand that CNC milling will Route the Pad/Trace/etc Contours without User Needing to do anything special…

Example: I did Not fuss with this, I just grabbed some footprints and placed them on PCB and added some Traces on the Bottom. Added one Via. NOTE: You can see that ‘my custom footprints’ have bigger, oval pads (the crude small ones are Stock and look worse in Graphics than they actually are when machined. I LIKE BIG PAD’s. Oh, and the Graphic’s of the “Hole’s” does Not reflect that I use the Drill-bit I want but, I leave the Default holes size as-is…

Summary: No need for Filled Zones (the stock PCB has them, that’s why we use them (unless you want to do your own Cu Plating!)

RESULT’s in CopperCam

[paulvdh]

I’ve been tinkering a bit with an example, and I think I managed to get something usable. I first made a little bogus schematic, just to have something to put on a PCB:

Then I designed a footprint for a DIP8, and I made pads with both an SMT pad on the bottom layer only and a NPTH hole. And then I put it on the PCB to see if it works. I also put a copper pour over the whole front of the PCB.

The front looks like:

And the back:

With the way I designed the footprint, DRC is mostly OK with it, but there are has a few problems.
One problem is that the center of the SMT pads can not be reached, because it’s in the hole, and this makes it a bit difficult to connect tracks to the pads. A way to circumvent it is to first draw a track segment, and then move it over the pad (or just copy some existing track segment).

The other problem is with the clearance. DRC complains about the hole clearance. But that is relatively easy to fix by setting: PCB Editor / File / Board Setup / Design Rules / Constraints / Copper to Hole clearance to zero. After that change the only complaint by DRC is about some silkscreen thing for another footprint, and there is something with the schematic parity, but I have not looked into that.

I’ve attached the test project below, I hope you find it useful.

2022-08-02_asdf_Dip8_SingleLayer.zip (21.1 KB)

Some other things to consider:
KiCad can generate a “drill map” file, and this groups holes with specific diameters. You can make use of this by using specific hole sizes for specific purposes. For example if you want to make your own via’s and want to use those hollow staples, then use a specific drill diameter for that, and make sure that drill diameter is used nowhere else.

I made the footprint in KiCad’s footprint editor, but started with the wizard for a DIP package. Those wizards are quite simple (a few pages of code) Python scripts. If you want to continue in this way, then I suggest you make a copy of that script, and then modify the copy so it generates pads with all the right properties.

[UgaBuga]

I can’t get rid of the clearance, and it’s not just a DRC problem, I can’t get the pads to connect. (Though I did set that setting to 0). This is what it looks like for me, I want pad 2 connected solidly to the fill around it:

What am I doing wrong?

[paulvdh]

1. Download the example I made.
2. Look if it’s what you want, test DRC etc.
3. Modify the example I made. Do you encounter any problems with it I have not mentioned?
4. Are there things you want differently?

The biggest advantage of working with that example is that I know what’s in it, (and anyone else can have a look too) so then at least we know we’re talking about the same things. A screenshot has much less info then a KiCad project.

[UgaBuga]

your example does do what I want, but I can’t reproduce it on my own project. I will try to go through each setting to figure out what’s going on.

[paulvdh]

Good to hear (read) some confirmation.
I did quite some fiddling with pad settings to get it to something I thought you wanted. You should be able to compare the footprint I made with what you did in your own project.

[UgaBuga]

correction, your example has the same problem if I add a copper fill on the back side:

I guess that’s because the fill can’t reach the center of the pad it won’t connect. Maybe I can manually connect to the edges of each pad. (If you make the pads big enough compared to the hole, it does reach them - you can see that your ovals are connected only on the long side because of the Clearance of Doom).

[UgaBuga]

I think I got it! Setting the fill clearance to zero finally connects properly:

I think this is workable. Thank you everyone!

[paulvdh]

@UgaBuga

I think I got it! Setting the fill clearance to zero finally connects properly:

Where is that fill clearance? Is it in the zone properties, board setup or somewhere else?

[UgaBuga]

It’s in the copper zone properties → settings pane → clearance. Makes sense that would try to stay clear of NPTH in retrospect!

[UgaBuga]

And also, @BlackCoffee, I think you’re not seeing the issue because you are not trying to use Kicad to validate your layout? If you’re not using filled zones it should mark all the grounds in your example as disconnected, and my guess is you don’t care about that (or did I miss something?)

That’s not a problem if one side is a solid ground plane, but on double sided boards you’ll have many small disconnected islands and I need CAD to help me figure out where and how many vias to place.

[BlackCoffee]

You are ‘Correct’. I don’t use or care about DRC. I have full flexibility doing layouts (doing it as I stated). All Grounds are connected (and isolated from the Stock Ground-Planes EXCEPT on Via’s). Residual islands are irrelevant - I place Via’s where needed and they don’t get isolated - It’s my Choice when setting-up the Milling process. And, normally, when I use Vias, I don’t actually use Vias - I just make a tiny NPTH hole - just like as shown for the big Hole. Thus, Top and Btm Cu is connected…

[UgaBuga]

Your boards must be pretty simple then, or you are a design genius. I have a relatively simple circuit with ~40 components and I need about 30 vias. No way I can afford to do continuity tests mentally

[Piotr]

@UgaBuga

but on double sided boards you’ll have many small disconnected islands and I need CAD to help me figure out where and how many vias to place.

It looks that you assume that 2 layer board means no solid ground plane.
That sounds surprising to me as since many years all my designs are 2 layer boards with solid ground plane at bottom.
In my case it is possible thanks to:

• using microcontrollers in TQFP case. I went with VCC under TQFP and distribute it through all corners and all VCC pins if needed. So VCC generally don’t disturb other routing.
• powering ICs by ferrite bead. Lefts extra ways to cross signal with VCC line.
• using small resistors (47…100) in digital lines to smooth the slopes.
• if can’t avoid crossing I prefer to use 0R instead of breaking my solid GND.

In typical PCB I need no 0Rs. The highest number of 0Rs used because of routing I remember is 3. It is at PCB I showed its fragment here:

Approaching PCB track routing for a newbie

Positioning for me is the main work in designing PCB. If each element is where it is needed than routing is simple. Till now all my PCBs are 2 layers and all of them have GND plane taking 100% of bottom layer. So except GND I design my PCBs as 1 layer. I use microcontrollers in QFP packages without thermal pad at bottom. This allows me to go with VCC under the microcontroller and go out through all corners and all VCC pins. That way GND and VCC don’t disturb my signal connections. At all digi…

All vias you see there are GND. You can find there something looking like track ended with via but it is also filled zone. When I posted that I thought you can see 2 0Rs there, but there are 3 of them. Right top of microcontroller (over 3 tracks), right bottom of microcontroller (over 2 tracks), and to VC1 track.
So all my vias are used to connect GND pins to GND and to connect GND islands on top to solid GND at bottom. If I were designing home made PCB without metallization I would probably not used GND zone at top at all as it is only a problem to connect all that islands.