Holes in multi-layer boards

I think that KiCad is an excellent software. However, there is one thing, or two things, I think is/are missing:
The possibility do define different pad and via sizes/shapes in, at least, outer and inner layers. For example, I want a via between the outer layers to not “perforate” copper areas (e.g. GND, VCC, etc.) too much. Typically, e.g., assume a TH pad with a 0.6mm hole diameter. For solderability, I might want an annular ring of 0.5mm in the outer layers but 0.15mm in the inner layers. I would also appreciate an option to suppress a pad in the inner layers when it is not connected there, so that the clearance is from the hole wall, not from a pad.
A possibility yo define the size for each layer separately would of course be even better, but I would “get on fairly” also with only onde definition for the two outer layers and one for all the inner layers.
I am presently using “good old” PCAD2006. “He” has the possibility to define pad shapes/sizes for each layer separately, but not for the suppression of unconnected pads. I fix this myself by defining the sizes in inner layers for vias as + 0.001 mm. Only these pads have such “uneven” diameters, After generating the Gerbers, I post-process them in with a program I have written myself, Post processing includes removing these “un-even”-sized pads from the Gerber files. The via WILL be connected to copper areas because of “direct connection” for vias.

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Is it possible to manufacture?

Yes, it is. It is the same as “saying” that the pad diameter is equal to the final hole diameter + 1 micron.
I have done so on a board.
Let me illustrate with an example.
Hole diameter 0.3 mm
Clearance 0.2 mm.
Minimum annular ring 0.2 mm.
I define the pad diameter 0.301 mm.
The following happens at the Gerber generation;
A “hole” with a diameter of 0.701 (pad diameter plus twice clearance) is generated in the copper area.
A pad with a diameterof 0.301 mm is generated as an “island” in the hole. This would imply an annular ring of 0.5 microns. It IS impossible to manufacture such an annular ring of 0.5 microns. These 0.5 microns of copper would be “torn away” at the drilling. My program removes the 0.301 mm pads from the Gerber file. The diameter of the hole in the copper area will be 0.701 mm instead of 1.001 mm at aminimal annular ring ov 0.15 mm, 1.101 mm at a minimum annular ring of 0.2 mm, etc.
It could, btw, be a good idea to add another (multiple of) 10 microns to the (ficticious) pad size, for another (multiple of) 5 microns of clearance.

The workaround is to have a THT pad with the smaller diameter, then add SMD pads on top and bottom layers on top of the hole. It should work well and is enough for THT pads where all inner layer rings are identical and smaller than the outer rings.

This feature is in the nightly builds and will be part of 6.0.


Brilliant! When can I expect 6.0 to be available?

There is no such thing as a concrete release date, but there is hope that the first release candidate for 6.0 should be available early next year. But, I’m not plugged into the development circles, I’m basing this estimate on what was discussed at the developer’s Q&A as part of the virtual KiCON last month and my poor memory.

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