This is something for the wishlist. I would like to hide PWR_FLAG when printing a schematic, because it does nothing and just confuses the readers. Would be great if this was implemented in the future.
Can’t you just place it off-sheet?
Not if it should be useful to be honest. Power flags should really be placed as close as possible to the true supply of the pcb. (Meaning: Do not simply connect your power symbols to the power flag.)
Connect it directly at the pin of the connector that supplies the board. Or directly at the output pin of the passive component in the supply line (example fuse or inductance of a filter)
I wonder if @LooZee uses power flags a bit strangely. If it is used correctly then there would not really be a need to hide it as it will add additional useful information to the schematic.
Hint: You don’t really use this symbol as intended if you simply place it such that ERC shuts up.
Is there some examples of the correct use of the PowerFlag? Thanks.
p.s. I use them as recommended in the documentation, but it always raises question:
That example is not really good to be honest. Well maybe i will look into that this weekend.
A far better description is found in our FAQ: ErrType(3): Pin connected to some others pins but no pin to drive it (Might also benefit from a larger example.)
I agree with Rene, use it as a help (“power enters board here”) rather than to satisfy ERC.
My post was a more direct answer along the lines of “If you really must hide it, this would be an option.”
It’s true, I mostly use them to satisfy the ERC, so PWR_FLAGs are usually added as a last step and when there’s no space reserved for them, it disturbs the look of the schematic.
My schematic has the battery or power connector on it, there is no need for further distraction. The ERC may need additional information, but a human won’t.
Putting them off-sheet is more of a hack, I think. Not really acceptable
I would not call the powerflags “useless”, they enable more rigorours ERC checking.
And with a littlbit of thought on where you put them, they just blend in logically with the schematic.
Here is a screenschot of the power setion of one of my schematics, and it has 3 power flags. 2 near the RJ45 connectors, where power enters the board and one on the output of the MP1584, which is a small 24V -> 5V SMPS. and the’re hardly noticable. The output of the AMS1117 does not need a PWR_FLAG because the power output in is already defined as a power output.
If you really don’t like the power flags, you can simply omit them and not use ERC, but I don’t recommend that. If you think ERC and thus also PWR_FLAG’s are usefull, then use them
If you really do not want to show the power flags on your schematic, then you can simply define the pins of the power connector as power outputs, just like the output pin of the AMS1117 in my schematic.
“Define the pins of the power connector as power outputs”
Of course, THAT’s the correct way to do it! Thank you Paul.
I created a similar post with a similar comment and it was not well received by many members here. However, I wanted you to know that I agree; they are not needed to read a well drafted schematic.
The options are:
1)Delete them after running ERC and finalizing the schematic design. They can always be added back later if the design changes.
2)Modify the source symbol such that the pin/s that are applying power are set as Electrical Type of Output. For some symbols, such as batteries and USB connectors these probably should have already been set to output when they were added to the KiCad library.
The one issue with changing a the pin/s types of basic connector is that this changes the simplicity of the symbol library. As a user transitions to Atomic parts in managed custom libraries this becomes less of an issue. All that is needed is a workable approach that you can manage.
I also agree.
This is a case where the designer is being driven by the tool, instead of the tool being driven by the designer. In my opinion, it’s not a major flaw. If this bit of confusion and clumsiness is necessary for us to have a meaningful ERC, then I can tolerate it. But . . . . I’m not convinced the confusion and clumsiness is absolutely necessary for an effective ERC.
In Pcbnew, I can change a footprint without affecting other footprints of the same type and without changing the library. The change only applies to the current project and layout.
If that could be done in Eeschema with pin types, there would be no such issue. The process of transferring a symbol from a global library to a project specific library is quite cumbersome, while it’s just one click in Pcbnew to do that for a footprint.
It dawns on me that you don’t have to use the PWR_FLAG glyph if you don’t like it. Change the symbol to something that is subtle enough to not be immediately obvious. Maybe a small diamond similar to the size of connection dots? Or just a short line that can be rotated to be coincident with the trace.
That said. I agree with @Rene_Poschl on using the PWR_FLAG symbol as additional documentation in my schematics. Though, I have altered my symbol to have a slightly shorter glyph (to fit between two 0.1" spaced nets) and hide the text. I also never use a Power Output type pin on my component symbols. But that is me. I also think that everyone should be able to have their own style. I’d hate it if every novel was written in the style of J.R.R. Tolkien.
Nice anectode, thank you, but doesn’t help with the subject at all. PWR_FLAG is a hack in KiCAD that someone came up with to fix some problem that really isn’t a problem if you take a second to think about it. No other CAD software needs that.
But do those other CAD packages do ERC checking on the part that the power flags enable?
The simplest solution is to add the PWR_FLAG to GND and Vcc symbols, and from what I remember a program that I used before KiCad existed did it that way.
Problem with this approach is that you can check if all power pins are connected to the Vcc net, but not if the Vcc net is actually driven by a voltage regulator.
I’ve check some 20 odd IC’s in the Regulator_Linear library and they all have their output pin set to “Power output” type. When you use those you do not have to place the PWR_FLAG to satisfy the ERC checking rules.
I did agree that the PWR_FLAG could be made a little les obstusive, but upon checking I discovered this has already been taken care of and in KiCad V5 it is the same size as all the other power symbols. Just compare the screenshot below with the (older) screenshots above.
Well, I’d like to know how you came to this conclusion. As much as I do not like them on the printed schematic, I do not mind them on the monitor.
KiCad does many things differently than other EDA software; often for good reason.
Seems to me that this “debate” could be resolved one of two ways:
Provide a “Hide” checkbox in the PWR_FLG symbol’s properties page.
Create a new pin attribute “PWR_FLG” that can be attached to the pin on the upstream component. That attribute would be stored within the schematic (not the library symbol).
IMO, the requirement of a “Power Flag” to leverage ERC properly makes complete sense. What I find completely distasteful is forcing us to meet this requirement by adding a visible object to the schematic.
Please see my post here…