Hidden, mysterious 'IN' net connecting unrelated parts

I have a (hierarchical) sheet which thinks it has net named ‘IN’ defined somewhere I can’t find. It is also assigning this label to any wires connected to parts which happen to both have an IN pin.

Do pins of type ‘Power Input’ automatically create nets in the schematic with the same name? That would explain what I see but seems very odd and likely to often cause conflicts.

If not, how can I find out where the schematic thinks this net is coming from?

Details:

If i do a ‘find’ in the sheet for ‘IN’ it doesn’t find any labels, just the two pins on the two parts

I’ll note that I made the second of these parts by 'save as’ing the first in the symbol editor then changing its pins to match the device. My understanding is that this should have nothing to do with the nets in the schematic. But I’ll mention it just in case. The parts have other pins which are shared too (PGFB, EN/UV) which do not exhibit this behavior. The IN pin is of type ‘Power input’

Do pins of type ‘Power Input’ automatically create nets in the schematic with the same name?

Only if the pin is additionally set to “not visible”.
Maybe depending on kicad version (which version do you use?)

Look at kicad documentation , section symbol pins → electrical types: Schematic Editor | 8.0 | English | Documentation | KiCad

my personal workflow: use only generic input/output pins, ignoring power inputpower out pin settings. Additionally I have most ERC-checks for input/output connection disabled - either too many false warnings or too much effort on exactly building the symbols to the need of the ERC.

edit: if you are still struggling with the issue: create a project archive (from kicad main manager: File–>Archive project) and attach that to this topic. So some interested users may inverstigate more deeply.

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This explains it. There is a not visible ‘power input’ pin.

For the several physical pins are all functionally ‘IN’, I made the symbol with one visible pin stacked with other invisible pins. I had seen this recommended in other posts (though I know opinions differ).

Thank you for your other suggestions regarding pin labeling. I’ll think them over

It all depends on the priority of the use of schematic - to create a PCB and look neat or as an aid to a service technician who just has the printed schematic to work from and who wants to know where THAT pin goes.

Invisible stacked pins should usually be set to “passive” type.

See S4.3 Rules for pin stacking - Library Conventions | KiCad EDA

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