Help with JLCPCB settings

[Keith1]

Hello,
I am really new to KiCad and JLCPCB. I am using Kicad 7 and have managed to produce the schematic and the pub design. These parts were relatively straight forward. I am now ready to generate the Berber files to send off to JLCPCB to get the board fabricated. I will be soldering the components myself.

I have a few questions regarding settings in Kincaid for use with JLCPCB. apologies for the long question.

After reading the JLC website many times,I found there capabilities page and Made adjustments to the Kincaid board settings in PCB Designer as follows…

Solder Mask Expansion: changed from 0 to 0.05mm
Copper Minimum clearance: changed from 0 to 0.127mm
Copper Minimum track width: changed from 0 to 0.127mm
Copper min connection width: changed from 0 to 0.127mm
Copper min angular width: Changed from 0.1 to 0.3mm
Copper to hole clearance: Changed from 0.25 to 0.4mm
Copper to edge clearance: Changed from 0 to 0.2mm
Hole to hole clearance: Changed from 0.25 to 0.5mm
Silkscreen minimum item clearance: Changed from 0 to 0.15mm
Silkscreen minimum text height: Changed from 0.8 to 1.0mm
Silkscreen minimum text thickness: Changed from 0.08 to 0.153mm

Could anyone let me know if I have understood the JLCPCB settings correctly please.

Also when I go to the “Plot” dialog I get a message tat says “Global solder mask minimum width and/or margin are not set to 0. Most board manufacturers expect 0 and use their own constraints for solder mask minimum width”

I this something I should be concerned with and if so how do I fix it please?

I also see that JLCPCB expect the Gerber output to be say F.Silks and not F.Silkscreen as generated by Kicad. again is this a problem and how do I fix this?

Finally ( for now) I saw in a post on this forum from Jan 2021 that to generate the Gerber file I should Uncheck the “Use extended X2 format” and check the “Disable aperture macros”. Due to some issues on JLCPCB side. Is this still the case or has this now been fixed?

Many thanks in advance for responses and help. As mentioned, this is the first time using any of this software and PCB fabrication services so any help offered would be appreciated.

Keith

[gmc]

I’ve had loads of PCB’s made at JLCPCB and have always submitted boards with the default settings and never had any issues.

For the mimimum solder widrh error you are seeing, go to File / Board Setup / Solder Mask, Paste and make sure the values are zero.

I aways untick extended X2 format before plotting. I recall seeing issues as well many moons back so have always just left it disabled. My disable apature macros is also unticked - I think that’s default?

[Keith1]

Many thanks for the answers.

One or two more questions from today’s playing.

When I generate the gerber files, I get a xxxxxxxx-job.gbrjob file (which does not load in gerber viewer). Does this need to be sent to JLCPCB?

Also, when I generate the drill files, I get xxxxxxx-NPTH_drl_map.gbr and xxxxxxxx-NPTH.drl files.
Do both of these get sent in the package to JLCPCB.
(I also have the same two files for the PTH variant).

In Gerber viewer, the gbr drill files show as X and O where as the drl files show as round dots of the appropriate size, is this normal?

Thanks again

Keith

[gmc]

Here’s a copy of the files I send through in a zip:

[OscarTheGrouch]

Same as gmc, I have just had JLCPCB make 5 PCB’s for me. Used default settings and included the files gmc listed, you do have to zip them.
OtG

[Martinn]

There are at least two plugins generating correct JLCPCB files. One is the “fabrication toolkit” in the plugin manager. No need for zipping.
Also… are you sure you want to hand solder your board? Try their PCBA service!

[gmc]

I’ve looked at their assembly service a few times and if you use any extended components it starts getting expensive.

[Martinn]

$3 per extended part type.
I try to use their basic parts mostly and you get quite far with those. You can also place all jellybean components (chip resistors and capacitors) and hand solder the rest, saves you a lot of work if you don’t have to fiddle all 0402 100 nF into place.

[retiredfeline]

@Keith1

When I generate the gerber files, I get a xxxxxxxx-job.gbrjob file (which does not load in gerber viewer). Does this need to be sent to JLCPCB?

No, they do not require the job file. You can turn off its generation.

@Keith1

xxxxxxx-NPTH_drl_map.gbr

Drill map files are not required, only the 2 drill files. You can also not generate the map files.

And the exact naming of the layers doesn’t matter, they can work out which is which, and even if you use the Protel naming scheme. If not they will contact you.

[greg_m]

I have a template based on 1-2 layer JLCPCB and PCBWAY settings (works for both). I can send you that if you want.

[Keith1]

Thanks for all the replies, it really helps to understand how all this fits together.

My board is basically a matrix of 3mm through hole LEDs hence me hand soldering. I will certainly look at SMT components on a future board.

One stupid question I have is placement of the board on the PCB design page in kicad. I have placed it in the center of the screen at (143mm,72mm). I assume this is ok and I do not have to position it at (0,0). It sounds a silly question but just thought I would ask.

[retiredfeline]

It does not matter. But because I’m a bit obsessively neat I roughly centre it on the sheet. But that doesn’t matter either.

[maqifrnswa]

I’ve been looking in to this too, and it is a little confusing since jlcpcb has 3 different constraints for things that KiCad has only one entry for. I agree with everyone that you would be safe just using KiCad defaults. That said, I’m interested in trying to translate the specs to Kicad. I interpreted the a little bit differently, but admit that there’s a good amount of space for interpretation because of the multiple definitions (e.g., three different minimum annular widths for vias, npth, pth).

Solder Mask Expansion: changed from 0 to 0.05mm

I believe you’re making a 2-layer board. 4-layer boards are easy (zero for these values), but 2 layer boards can be a little tricky because jlcpcb’s diagrams can be confusing (at least to me). I think the “correct” value would be a soldermaks expansion of 0.038 mm for a 2-layer board. If you use something too large, you risk exposing copper on your traces (Soldermask Expansion - funwithsoftware.org). the 0.05 mm you saw is actually something else: that’s basically saying that your trace to pad clearance should be greater than (0.05 mm +solder mask expansion), I believe.

Copper Minimum clearance: changed from 0 to 0.127mm
Copper Minimum track width: changed from 0 to 0.127mm
Copper min connection width: changed from 0 to 0.127mm

looks good

Copper min angular width: Changed from 0.1 to 0.3mm

Maybe should be 0.13mm – that’s what they define for annular ring. If the minimum annular ring is too small, the DRC might yell at you for every via smaller than (drill hole +0.6mm) in diameter (which would be every via, most likely). There’s a little confusion since KiCad only has one minimum annular ring, but jlcpcb has 3: minimum annular ring for vias is 0.05 (recommended 0.075), for other holes is 0.13, and for PTH is 0.3mm. So if you’re just using the minimums for the DRC, you could even put the minimum annular ring to be 0.05, or run the DRC 3 times, each with a different value. So this one is “complicated/unclear.” Practically speaking, even the vias should respect the minimum annular ring (as it takes in to account a bunch of fab tolerances), so making it 0.13mm is probably a good idea.

Copper to hole clearance: Changed from 0.25 to 0.4mm

I think they say it’s 0.254mm? NPTH and via to track are both 0.254mm. PTH is 0.33. So you can put 0.33mm to be safe, but probably the “minimum” might be 0.254mm, so keeping the KiCad default should work.

Copper to edge clearance: Changed from 0 to 0.2mm

looks good

Hole to hole clearance: Changed from 0.25 to 0.5mm

jlcpcb has two different minimum values: one for vias (0.254mm) and one for other holes (0.5mm). I might suggest keeping this 0.254mm clearance as most (all?) of the holes that the designer adds will be vias. You can run the DRC twice with two different settings if you really want to be careful.

Silkscreen minimum item clearance: Changed from 0 to 0.15mm
Silkscreen minimum text height: Changed from 0.8 to 1.0mm
Silkscreen minimum text thickness: Changed from 0.08 to 0.153mm

Looks good