Help with 8-SOIC Power Pad's exposed pad

I hereby certify that I am not simply asking someone else to design a footprint for me.

This is an auto-generated message that is in place on the “footprints” section of the forum. If I remove it and ask for a footprint to be designed anyway, I understand that I will be subject to forum members telling me to go design my own footprint or referring me to a 3rd party footprint site.

I’m using the LM7372 dual op-amp as part of my circuit, specifically the 8-pin SO PowerPad package. Rather than design my own, I thought to use a pre-built model from Digikey as shown in the picture below. The measurements match up, as well as TI’s 3D model, so I thought it would work well. The problem I’m facing is how to implement the exposed pad in the middle.

On the part’s datasheet below, page 3 says that the exposed pad should be tied to V- or left electrically floating. The same holds true with their 16-pin SOIC for their heatsink pins (1, 8, 9, and 16). Now, following their instructions, I would like to connected it to a floating piece of copper (a copper island). You can see how they did it with the 16-pin SOIC on page 17 as an example, but I was wondering how to implement it in KiCAD?

The component is on top of a ground plane, and when I add a copper pour and tie it to the op-amp’s center pad via its net name, nothing happened. I was expecting for the copper zones to allow for some clearance and leave a floating copper island, but it didn’t. For people who have seen these components before, how do you properly implement it in KiCAD?

Datasheet: TI Datasheet

I guess this is a symbol you made yourself? So as stated in the KLC, you just need to match up the symbol with the footprint.

Thanks for the reply. Turns out, it’s not the footprint per se…it’s a combination of the zone priorities (with both zones being priority 0) and the pad connection to zones which are not giving me the results I wanted. Increasing priority forces KiCAD to create my ‘isolated copper islands’, so that works well, though I had to set the pad connection to zone for Pad 9 above to ‘Solid’. Not sure why this is necessary though.

If I may ask, since we’re on the topic, I was wondering if I did this right. To be clear, I’m not asking for anyone to make a footprint for me, but to critique my own footprint. Thinking about it, I’ve decided to make my own custom footprint following TI’s datasheet for their 8-SOIC PowerPAD package, and I was wondering if I did the center pad correctly. You can see my design in the picture below.

Looking at their datasheet, in my view, they seem to show a center copper pad of 2.95 mm by 4.9 mm with drill holes among them, and that copper pad is exposed to the outside world via solder-mask clearance. Since the clearance isn’t proportional, I did two things. First, I made the larger copper pad in the center and made sure that no technical layers were checked. Next, I created a second pad (with the same pad number) and made it 2.71 mm by 3.4 mm, and I made it such that it is only on the solder-mask layer with no copper layer present. Then, I just put them in the same spot at the origin (0,0). Regarding the holes, they are through-hole pads, with the hole size and the (size X) the same, so there’s no annular ring.

You can see the result in the 3D view. To me, it looks correct, with the larger copper square covered with solder-mask, and the exposed copper in yellow. But is this correct? Is this the correct way to design such a pad?

SOIC_PowerPad.pdf (61.8 KB)

Yes, that appears correct to me.

Thanks. Never worked with the part before, so I’m just trying to make sure it’s correct. Feels like it’s gonna be a pain though if not done correctly.

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