Help needed with DRC rules (KiCad 5.99)

In this situation

I want to detect the silkscreen-to-via overlap. Silkscreen is a filled rectangle.

I’ve the rules below. Refdes and other text is caught all right when overlapping, but not the filled silkscreen rectangle overlapping the via

(version 1.0)
(rule silk2via
(constraint silk_clearance(min 0.15mm))
(condition “A.Type==’*Text’ && B.Type==‘Via’”))
(rule silk2via1
(constraint silk_clearance(min 0.15mm))
(condition “A.Type==’*graphic’ && B.Type==‘Via’”))

It’s good to mention this is for 5.99 only, not for v5.1.

Ok. Changed the title. Any idea about the issue?

I’m not at my own computer now, I can try to think about this later if anyone else doesn’t. @JeffYoung is an authority on the DRC rules.

Fair enough. Thanks.

Try “Graphic_Shape” (or “Graphic*”).

Property map for A.Type:

            .Map( PCB_MODULE_T,         _HKI( "Footprint" ) )
            .Map( PCB_PAD_T,            _HKI( "Pad" ) )
            .Map( PCB_SHAPE_T,          _HKI( "Graphic Shape" ) )
            .Map( PCB_TEXT_T,           _HKI( "Board Text" ) )
            .Map( PCB_FP_TEXT_T,        _HKI( "Footprint Text" ) )
            .Map( PCB_FP_SHAPE_T,       _HKI( "Graphic Shape" ) )
            .Map( PCB_TRACE_T,          _HKI( "Track" ) )
            .Map( PCB_VIA_T,            _HKI( "Via" ) )
            .Map( PCB_MARKER_T,         _HKI( "Board Marker" ) )
            .Map( PCB_DIM_ALIGNED_T,    _HKI( "Aligned Dimension" ) )
            .Map( PCB_DIM_ORTHOGONAL_T, _HKI( "Orthogonal Dimension" ) )
            .Map( PCB_DIM_CENTER_T,     _HKI( "Center Dimension" ) )
            .Map( PCB_DIM_LEADER_T,     _HKI( "Leader" ) )
            .Map( PCB_TARGET_T,         _HKI( "Target" ) )
            .Map( PCB_ZONE_AREA_T,      _HKI( "Zone" ) )
            .Map( PCB_ITEM_LIST_T,      _HKI( "Item List" ) )
            .Map( PCB_NETINFO_T,        _HKI( "Net Info" ) )
            .Map( PCB_GROUP_T,          _HKI( "Group" ) )

Would it be better to ignore the case of the property? I know that later it won’t be done like this but still would help.

Yessir :slight_smile: Works now.

Thanks for the map. I had no more info than the types listed in help.

Beeing greedy: is there a possibility to define a severity in the rule’s conditions?

IMHO, this silkscreen-to-via overlap should be included in the built-in DRC, and not require a custom rule. Unless I misunderstood the intent, these custom rules are designed to check conditions that are very specific to a project. Checking if silkscreen overlaps a via applies to any project (probably with a Warning severity).

… or the chosen boardhouse’s requirements.

@JeffYoung I commented out a rule (Ctrl+/), but it is executed regardless. Bug or PEBCAK?


Case is ignored. (The problem was that our adjectives are on opposite sides so the text wildcard needs to go before “Text” while the graphic one needs to go after.)

Sounds like bug…

(Seriously? “Post must be at least 20 characters?”)

@JeffYoung Should I open an issue? Btw, this 20 character thing annoys me as well at times.

Yeah, please do. I’m knee deep in the zone filler right now…

I fully agree. Silk-to-silk, silk-to-pad and silk-to-via/THT/hole should be built-in, there should be constraint settings in pcb setup and entires in the violation severity to go with it.
If you feel like it, you might want to go ahead and open a wishlist issue in the bugtracker.

Actually, silk-to-silk, silk-to-pad (THT or SMD) and silk-to-hole are covered (with the “silk clipped by soldermask” rule for the last two) by the current built-in rules. I will open a wishlist for the silk-to-via overlap only.