IMHO, this silkscreen-to-via overlap should be included in the built-in DRC, and not require a custom rule. Unless I misunderstood the intent, these custom rules are designed to check conditions that are very specific to a project. Checking if silkscreen overlaps a via applies to any project (probably with a Warning severity).
Case is ignored. (The problem was that our adjectives are on opposite sides so the text wildcard needs to go before “Text” while the graphic one needs to go after.)
I fully agree. Silk-to-silk, silk-to-pad and silk-to-via/THT/hole should be built-in, there should be constraint settings in pcb setup and entires in the violation severity to go with it.
If you feel like it, you might want to go ahead and open a wishlist issue in the bugtracker.
Actually, silk-to-silk, silk-to-pad (THT or SMD) and silk-to-hole are covered (with the “silk clipped by soldermask” rule for the last two) by the current built-in rules. I will open a wishlist for the silk-to-via overlap only.