Having multiple clearance for the same net or how to split a net?

Layout
1

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Please refer to the image, I have three impedance tracks on pin 3,9 and 14

Please refer to recommended footprint dimensions.

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Attached is the footprint

QFN16_rfaxis1010.kicad_mod (2.4 KB)

I only have two net classes

Default with 0.21mm clearance and 0.21mm width
For RF track 0.366mm width and 0.25mm clearance.

Can you let me know what is incorrect with the foot print or if the error is else where can you please point out.

** Found 5 DRC errors **
ErrType(19): Pad near pad
@ (145.600 mm,98.250 mm): Pad 3 on F.Cu, Non-copper of U2
@ (147.000 mm,98.000 mm): Pad 17 on F.Cu, Non-copper of U2
ErrType(19): Pad near pad
@ (145.600 mm,98.750 mm): Pad 4 on F.Cu, Non-copper of U2
@ (146.250 mm,99.400 mm): Pad 5 on F.Cu, Non-copper of U2
ErrType(19): Pad near pad
@ (147.000 mm,98.000 mm): Pad 17 on F.Cu, Non-copper of U2
@ (147.250 mm,96.600 mm): Pad 14 on F.Cu, Non-copper of U2
ErrType(19): Pad near pad
@ (147.750 mm,96.600 mm): Pad 13 on F.Cu, Non-copper of U2
@ (148.400 mm,97.250 mm): Pad 12 on F.Cu, Non-copper of U2
ErrType(19): Pad near pad
@ (147.750 mm,99.400 mm): Pad 8 on F.Cu, Non-copper of U2
@ (148.400 mm,98.750 mm): Pad 9 on F.Cu, Non-copper of U2

** Found 0 unconnected pads **

** End of Report **

Can I create multiple clearance for the same net in case of RF tracks, if that is causing the DRC violations?

2

the pads are at the corners…
4/5
8/9
12/13
probably lacking vis-a-vis distance to satisfy clearance

Either modify the clearance, the footprint or use the latest nightly version with round cornered pads.

Interesting that the OpenGL version differs from the legacy version in this regard (BZR6971):

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these pads have tracks going to them while the width changes…
3/17
14/17
no idea, but maybe the clearance settings for the thinner tracks then get ‘screwed’ up and cause problems?

0.25 mm clearance from the RF track is just about the distance from pad-edge to pad-edge… try 0.24 mm for that track width in the design rules to test and re-run DRC… if it’s gone you know that this is the culprit and can work on the problem.

3

I have tried reducing the RF track clearance to 0.23 and it makes no difference.

However when I move the corner pads by 0.02mm the error goes away

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I will modify the footprint to change the overall length from 3.5 to either 3.54 which will be still with in the tolerance level which will space out the pads at the corners

4

OK, sounds good, not satisfying but workable I guess.

5

I think KiCad’s reporting coul be improved here,
Serving up a glib Pad near Pad message, that lacks numbers is less helpful that if could easily be.

DRC must know the actual clearance - why not tell the designer that ?!

Also, DRC must know what rules were applied, to trigger the error, and again tell the designer that

Suggested improvement
**ErrType(19): Pad too near pad, 0.2212mm < 0.25mm
@ (145.600 mm,98.250 mm): Pad 3 on F.Cu, Non-copper of U2 Net Rule 0.25mm
@ (147.000 mm,98.000 mm): Pad 17 on F.Cu, Non-copper of U2 Net Rule 0.21mm

6

Many thanks for the feedback.

I just came across a solution without changing the pad position

I changed net pad clearance on the Pad 3,9,14 which were using the netlist clearance.

I use the pad level netpad clearance and changed its value to 0.21 and this removes the DRC on those pins.

However the corner pins 4,5 and 13, persist with the non copper error even with a pad level clearance of 0.21. Those errors disappear if I change the pad level clearance on those pins to 0.14 - however the board manufacturer tolerates only 8mil or ,20mm minimum pad distance. I don’t see this possible without moving the pads

7

I found this land pattern from Vishay which has more space for the corner pins

my package dimensions are as below, do you see any problems using the above foot print

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8

I ended up creating a new footprint as neither the Vishay/OnSemi or Linear PCB foot prints satisfied a 0.2mm pad clearance at the corner - this put to rest all DRC problems