When creating a hatched copper layer, some of the opennings created in the copper layer to form the hatched pattern are below the minimum possible by our manufacturer. In addition, this is also an issue when traces on the same net go through the hatched plane. How can this be avoided? See some examples below. Thank you!:
I never used hatched copper and never thought about it.
If the goal is to equalize the amount of copper on both sides of the board then perhaps hatched fill is intended to be used outside of any traces or footprints.
Don’t use it, or use another fab.
What’s the use of it? Some sort of primitive Faraday cage?
I think the bigger problem here are the TINY vias. Why are there so many absolute tiny vias around the ground plane? If each of them has a drill diameter of 0.2mm or less, then it won’t be manufacturable. Best would be to use 0.3mm drill size and 0.6mm annular ring.
I think the small areas in the hatch are not the problem here.
Besides that, hatched copper has probably no benefit for your use case. If you did not design a flex PCB, a normal copper pour would suffice.
Thank you all for your comments. The hatching is required by the manufacturer to ensure specific copper density in each layer for manufacturing reasons. This is a specialized process with 35 um via holes, no other via hole diameter is allowed. Using another fab is not an option. I have already manufactured a previous version that works perfectly fine. The small area in the hatch is the problem. I had to manually fill the problematic areas in the hathched planes in the previous design and I want to avoid doing this. I am hoping there is a automatic way to do this rather than doing manual corrections. To somehow fill the gap if below a certain limit, automatically by the routine.
I fear that this is not possible. KiCad probably is not the right tool for boards that need such advanced features. Even tough I don’t get why there is a requirement for 35um vias, but I know nothing about your project
The via hole diameter needs to be equal to the supporting polymer thickness. It has to do with the electrochemical step that fills the hole with copper to connect the copper layes on each side. Yes, it is a very specialized process not widely available, for niche applications.
Oh, so you want to basically mspaint style fill the smaller gaps, yes?
I ideally want this to be done automatically, when creating the hatched fill. I want to avoid filling the problematic gaps manually one by one.
I ideally want this to be done automatically, when creating the hatched fill. I want to avoid filling the problematic gaps manually one by one.
This is not possibly with the current kicad version.
But normally it poses no problem if the manufacturer is not able to produce these small openings:
- if the etching process works exactly you will get the openings
- if the etching process works not exactly the opening is not etched - you get a closed fill. Just with your solid painting.
So either result should work (technically). You just have to tell the manufacturer to ignore the "too small"warnings.
Thank you @mf_ibfeew for confirming. I was hoping that maybe there was a way that I wasn’t able to find. Unfortunately, the fab house cannot ignore, so in the previous run I had to work with them to identify the problem areas and to then manually fill.
What is the task of series vias around pad 5 while pad 5 is connected to them only by 4 thin thermal relief connections?
May be the fill area line around this pad will not be generated if connection will be ‘solid’.
The zone filler does not account for things like tracks running through the fill area today. Could you open a feature request for this if you need it?
That said, this also seems like the kind of thing that the fab should be used to cleaning up in their CAM software.
Thank you @craftyjon for also confirming this. Yes, I did start a feature request thread. Unfortunately, the fab is not very happy about this. From what I understood after speaking with them, other commercial design tools have more advanced hatching capabilities that avoid these issues.
If you mean here on this forum, that’s not what I meant. Feature requests are made on Gitlab as issue reports. This forum is not an official place to ask for changes to KiCad.
@Piotr thank you for the proposition. The problem areas are not related with whether there is a thermal relief or not. Using a solid connection does not fix the issue. This was just an example. This was actually an old image, the design has been updated and indeed the connection to the pad is solid, no thermal relief. This is a 10 GHz board design, so the board is pretty much covered with via to GND to reduce the inductance to GND. Here is the same section with solid connection to the pad.
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It’s a bit manual, but when you’ve finished routing, you could use a keepout area in the problem bits / around the traces to remove the extra zone fill bits.