Please give a link to the antmicro project and we can open it and see how it’s been done. Or better yet, you can open it yourself and see how it’s done.
Probably the big question is can PCIe 3/4 routing be done with simple length matching, or is time-based length / skew tuning needed? Still digging as my first foray into this …
PCIe does not require aggressive length matching at all (only intra-skew, careful impedance check for 3/4+, including common mode impedance continuity), timing-wise it’s self deskewing… Just look at any PC motherboard.
I’ve done a thunderbolt design (passive adapter only), and a bunch of HDMI and DisplayPort things (with redrivers, muxing, lots of links on one board, high double digit diffpairs per board etc). HDMI is much more of a pain than PCIe in terms of signal integrity. KiCad is totally fine for these designs. The curved traces you see are probably done with the fillet tool. Other people do way bigger designs with KiCad with high layer counts and hundreds of diffpairs per board and it works out. The biggest problem at the moment is the inability to rework (parts of) diffpairs by dragging them after the fact - you have to delete part of the route and redraw that segment. This is intended to be fixed in v9 but it’s an issue now. It’s also more difficult than it needs to be to manage the design rules for high complexity designs. But should be no problem at all for PCIe.