DRC has greatly improved in KiCad V5.99 and there are now a long unsorted list of nearly 40 settings for severity of DRC errors in Pcbnew / File / Board Setup / Design Rules / Violation Severity
A few days ago I opened an Issue on gitlab for this and I made a suggestion by ordering them by object type.
Jeff Young made a suggestion to sort this list as:
electrical (mechanical tuning and schematic parity (or something similar)
Jon Evans made a suggestion for these categories:
Clearance / shorting DFM (hole size, board edge clearance, footprint collision, etc) Signal Integrity (diff pairs, skew, etc) Other (schematic parity, problems with footprints, etc)
I am getting into trouble when trying to sort the items by function type.
For example, “Track width” is both a signal integrity issue and a DFM issue.
So the question is, what would be the best categories and sorting order for DRC violations?
If you want to give it a try, then copy and edit the text below for the order you would like best, or if a few suggestions are posted. Make a vote for which you like best and a short desctiption of the “why”.
Tracks
Track width
Track crossing
Trace length out of range
Track has unconnected end
Pad net doesn''t match schematic
Differential pair gap out of range
Differential uncoupled length too long
Skew between traces out of range
Vias & holes
Via is not connected
Via hole larger than diameter
Annular width
Too many vias on a connection
Micro via drill too small
Drill too small
Drilled holes too close together
Hole clearance violation
Padstack not valid
PTH inside courtyard
NPTH inside courtyard
Board and Area
Board edge clearance violation
Board has malformed outline
Copper areas intersect
Copper zone net has no pads
Keepout violation
Miscellaneous
Unconnected Items
Items shorting two nets
Items not allowed
Item on a disabled layer
Clearance violation
Unresolved text variable
Silkscreen overlap
Silkscreen clipped by solder mask
Note that I’ve checked in a cross between Jon’s and my original proposals just to have something. But it’s easy to change so don’t interpret that as it being a “done deal”.
IMO any of the above suggestions would be good. I wouldn’t split hair over it.
Right now it’s too chaotic; but whether it will be sorted by object or by violation type (with second order sorting by object type) it will be good improvement, and something we - KiCad users, will learn how to work with.
After doing the ordering of the list, usability wise it will be OK.
However the continuous list of Radiobuttons seems a bit weird, and it’s not common (at least in Windows).
Using something like Datagridview would be more native style of presentation, with user choice (Error/Warning/Ignore) as a drop-down select. Having implemented control like this, we could add columns for “Item” (Trace/Via/Footprint/Board/Other) and “Type” (Clearance/DFM/Integrity etc). Datagridviews allow to sort items, so anyone could sort this list as one needs (by object, by type or by severity). This would satisfy anyone’s tastes, but is it worth putting effort into? I’m not sure.
Highest priority violation on top? or bottom? Meaning
the first violation to be flagged by the DRC checker.
[quote=“paulvdh, post:1, topic:26292”]
Board has malformed outline [/quote]
This is probably an easy check if the user intends to create a rectangular board. (Just see if the diagonals are equal.) However, it is the test to see if this is true that bothers me. What if the user wants a board that is made of two rectangles, a big one and a little one, joined together along one edge of the little one?
I am not sure there could be a convenient test to see if the board outline is malformed . I’d rather just see a “check for equal diagonals” flag run by DRC for the simple case.
My best guess is that “malformed outline” means that end points of line segments on Edge.Cuts line up. KiCad doesn’t know whether you want to make a triangle or a pentagon.
But this thread is not about the contents of those violations, just about the grouping and ordering in the menu. Mr Young committed a merge, I’ll look tomorrow what it’s look like.
The malformed outline test doesn’t have anything to do with rectangles. It just checks all the lines, arcs, etc. to see if they connect to make an outline with optional holes. For instance, it will flag 3 sides of a rectangle (because the closing side is missing).
“Schematic Parity” indicates whether or not the PCB matches the schematic. In other words, are there footprints for each symbol and are they connected in the same way?
