Hello,
I’m new to PCB design and KiCAD. I would like to customize a PCB for a amplifier project, using the manufacturer reference design. The circuit is a double layer PCB, with ground pours on top and bottom. Both ground pours are connected by somehow 1000 vias. See image below.
Can those vias, associated with the ground pours, be generated automatically in PCBnew ?
Best regards,
JMF
There is a request for this feature in the develop issue track website
May exist some python script to do that.
The term you are looking for is via stitching. Kicad 5 has at least support for adding such vias. (In v4 you would have needed to use single pad footprints as a workaround.) As of yet there is no automatic way of creating such vias. (It was planned originally but it never got to that stage.)
You can however use the array tool to help you out and there area also some python scripts out there that can add things like guarding vias along a trace of interest. (I think @maui designed such a script. Not sure if it still works under v5)
@hildogjr
you may have a look at here:
@Rene_Poschl
regarding via shielding, I just merged benkempke code to my internal release of kicad, to have it
hope some dev will include those in kv6
@Rene_Poschl Can you clarify what you mean here?
@jmf11 For one design I was able to create stitched vias using V5, and I don’t remember it being that difficult; though I don’t remember the exact process I used.
Quite a few of the vias do not appear to be mathematically placed. Creating a grid and throwing the vias in manually would be a bit time consuming, but should not be unreasonable when combined with the other tools in PcbNew.
KiCad 5 has an add vias tool in PCBNew. Here it is on the tool bar:
But it is manual placement. If you place the vias on an existing net (either trace or zone) it will automagically connect to that net.
I’m not aware of any scripts (yet) that can automatically place vias. A script that would be good for this application (given the desired structure) is one that places vias at predefined intervals along lines in one of the documentation layers (one of the ECO layers?).
Okay, but I think one can “duplicate” many of them (keeping them assigned to the same net) and move them around; making the process a bit less time consuming.
Anyways, I don’t remember it well enough, but it wasn’t something that caused me such annoyance that I’d never forget the pain. Although, I only did ~36 stitched vias on a design, and not 1000+ as the OP estimates.
Thanks for all your advices and links. I will study all of them in details.
I have a bad habit when learning something, to starting from a real use case, of significant interest for me, to drive the motivation. Sometime the use case is a bit too complex for just learning…
I had identified that via stitching as “the specific feature” of my target design. Hence my questions.
However, I don’t know how important it is for the circuit performance this via stiching, knowing that the amplifier chip will operate at 600 kHz.
Best regards,
JMF
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