I am having 2 issues, and I’m sure one of you pros knows a simple fix.
I need to add an identical trace on the front and back copper for a high-current area of the board. I draw one no problem but when I draw the other one it automatically removes the first one. How can I keep both?
When I am making a ground plane it is shorting out an inductor. Is there a way to exclude a pad from the ground plane?
One thing…go to help>about>copy version info. Paste it into your next response.
This (from version 6.0) should help with one of your questions (from the route menu):
That solved the dual track, thanks!
I am running 5.1.9
If the pad is not connected to GND at schematic than ground plane should not short it.
May be it is a bug and may be it was fixed on the way from 5.1.9 to 5.1.12.
I agree and did not have a good answer to that question.
It shouldn’t happen. First update to 5.1.12
If it still happens, share your project, these problems are usually down to a hidden short on the schematic. Its easy to hide a “wire” under a component symbol
Thanks for the replies everyone. I will look for hidden connections and update as well. I’ll post an update next week
That has never happened to me so far as I can remember, but I do not use Phil (or his wife Joyce) on any of my symbols. 
Does symbol fill color help with anything other than cosmetics? Might it be true that it can obscure hidden wires?
My former neighbors Phil and Joyce do not live here any more so they will not mind my reference.
Nor me Bob, but we come from a time when schematics had to be drawn neatly
I have seen bridging several times on this forum and in my office, they don’t teach technical drawing at university these days
One of the steps I go through before adding fills and generating Gerbers is to use the Highlight Net function of pcbnew to check that every pad is connected to what it’s supposed to be. It’s painstaking but the alternative is a mistake that will take time and money to correct.
In the case of the ground and power nets it’s fairly easy to see if an inductor pad is highlighted when you select those nets.
I never done it, but when routing I always know what connection I am doing and I hope I will notice if any connection will be wrong. May be I can do that way because my schematics are rather simple - just input/output elements connected to microcontroller pins.
A behaviour of eeschema that irks me is that when I cut and move circuit blocks it can acquire junctions in the process of moving. Fortunately ERC usually catches this. One would think the lines should be deactivated from acquiring new junctions until the block is laid down. Maybe it’s better in 6.
Today my Highlight Net check found a footprint that was flipped. I had changed the footprint from pin header to just pads but the order of the pads was the other way around in the replacement footprint. That would have had the effect of flipping +5V and GND in the manufactured boards.
I assign footprint to symbol once and never charge it. If I want to use another footprint it has to get a new symbol also so I have to define that symbol. In a case of 2 x n connectors my symbols follow the way of numbering used in footprint. To do such replacement as you described I would have to change symbol at schematic and new numbering way will be inserted automatically. Even numbers will be changed no tracks change at PCB would be needed. I believe that this practice protects me against such mistakes.
So you do your extra work up front and I do mine at checking time, that’s all.
I should add that I was reusing an old project so I expected to have to check. Parts also were changed.
This is the issue, my workaround, and the schematic. I also just realized it removed a trace over to pin 2 on the -252 component on the left in the schematic.
I’m having trouble getting your PCB (and labeling) to match your schematic in my mind. The schematic seems to indicate the pin 2 output of the -252 device (looks to me like an adjustable voltage regulator, the “VO” and the “ADJ” pins look right for my guess) is going to pin 1 of the connector. This indicates to me that it should be some other voltage than GND, yet that is how you have the connector pin labeled in silkscreen. Also, you can see that the trace connecting the connector pin1 to L2 pin 1 is part of the GND net (which is why the copper fill tries to connect to those pins). But I don’t see any connection in your schematic to GND for that line (that you highlighted).
Are you sure that the board’s net information is up to date with the schematic?
This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.
