GNDA net changed to GND

[davidsrsb]

Running latest pre 5.1.6 Nightly on Windows 10 64bit (26/3/20 build)

I have a hierarchical design that I developed, passed to another user for update to V2 and I started work on it again after renaming and putting it into a new folder.

I updated the pcb from the schematic and found that the GNDA net and zones all renamed to GND
So I tried exporting a netlist and this also only contains GND
I have searched for GND in the schematic sheets using search and even using notepad++ on the files, but just cannot see what is triggering this.

I have tried a simple test project and GNDA is used, so it is probably not a bug

[qu1ck]

You must have GND flag or net somewhere tied to GNDA in schematic and kicad picked GND as net name.

[paulvdh]

As far as I know, when you connect 2 global labels together in KiCad, it just picks one of the net names.

I wanted to be sure so I cobbled together a little experiment:

Today KiCad decided that R1 is connected to “Left”.

I don’t know what it will do tomorrow.
All that the power (and GND) symbols do is connect a global label to the net that you draw on it’s pin. Simple and effective, just as I like it.

With local labels it seems to be the same in KiCad V5.1.5
When I disconnect GND from the resistor and add 2 local labels like so:

Then, while updating the PCB, I get:

[davidsrsb]

I have looked for the obvious case of a spurious GND power symbol. Unfortunately KiCad 5.1.x does not warn of the two nets connected case, which should really be an ERC error
I have also looked for symbols with hidden power supplies like the old 7400 series.

[BobZ]

I like Foo Bar…reminds me of a military informal code word…

[davidsrsb]

Solved it
I had created a 4 pin SOT-223 regulator symbol where GND pin 4 is a second 0V connection.
I had stacked the pins and made the hidden pin a POWER INPUT, same as the visible pin 2. I changed the hidden pin to PASSIVE

[paulvdh]

Glad you already found it!
I was just experimenting a bit with first:
Eeschema / View / Show hidden pins and then:
Eeschema / Edit / Find with the option Search all component Fields

[davidsrsb]

I really don’t like a hidden power input acting as a global label.
I guess that this was done as a kludge for the 7400 power pins

Worse that ERC does not complain that there is a second label trying to name a net

[paulvdh]

It looks like a leftover from the early dark ages of KiCad.
Would you want ERC errors if “GND” “Earth” and “GNDA” were connected together? Maybe net ties would have been appropriate here, but these are also still quite a hack in KiCad V5. It may have already changed in V5.99, or I will at least expect it to be implemented more logically in the future, and untill then, we’ll have to live with it.

See also this longish post I made for this new user, who had a more serious related problem.

Power rail is not connected in netlist output

Hi Sir I have created a simple shcematic in KiCad Eschema(sorry as a new user I cannot directly insert an image to show the schematic drawing here, see my next post below) When I export netlist(*.xml) of this schematic, it is strange that two power rails are not correctly connected in the netlist file Net name “USB_1P2” at the right-top circle the net is connected to “R4095” and “EC4902” at the middle circle the net is connected to “L4904”~“L4909” I would expect that in netlist file the a…

[janvi]

@paulvdh

Would you want ERC errors if “GND” “Earth” and “GNDA” were connected together?

Yes, if you name separate nets you should have a reason for. In case of analog lines I always use an inductor (or 0 Ohms Resistor) or for direct connections at least anything like footprint SolderJumper_2_Open to force star routing topology. Its also a good practice to have a virtual gap (in Soldermask) to isolate circuit parts. Those lines must not cross other traces or components except the additional components what tie two nets, optocouples or transformers.

[davidsrsb]

ERC warnings would be enough, let the designer decide if it was intended

[eelik]

@davidsrsb

ERC warnings would be enough

It’s been planned for v6 IIRC.

EDIT: see https://gitlab.com/kicad/code/kicad/-/issues/3980, but I just found out that the ERC dialog has been changed in 5.99 and I can’t find the ERC settings at all in the latest nightly build.