Hello all,
Im currently designing a PCB which controls a LED strip(WS2812B).
To program the MCU and for serial communication, im using a couple of pads. I intend to solder wires to the pads, then communicate with MCU through an Arduino uno.
How do i remove the copper design like this around this pad?
Is the PCB layout generally good?
Front:-
Thanks for all the help!
How do i remove the copper design like this around this pad?
I would try either with a:
The “Weird design around GND pad” is a part of a thermal relief that tries to connect to the GND zone around it. One way to “fix” it is to set the pad properties to not connect to the zone at all, and then draw a track manually.
For the rest, your PCB already looks better then what I see from most beginners. I see you used a 4 layer design. On a PCB as simple as this, a (slightly cheaper) 2-layer design is plenty, but 4-layer boards are much easier to layout then 2 layers, and it’s fairly common to see 4 layer PCB’s even when it could be done in two layers because it saves design time.
What is your layer stackup? It looks like the red front layer is connected both to GND and to +5V. And I can also only see 3 of the (presumably) 4 layers. What is your track width? Often, 4-layer boards are made on more modern machines, which have a higher resolution, and thinner tracks have less capacitance and are therefore better for most signal tracks. One thing that is quite important and easy to overlook is to how the tracks are referenced over their length. Simplest method is to have one single continuous GND plane. If you have multiple GND planes, then put GND vias where the signal reference changes. If the reference goes from a GND layer to a power layer /zone, then add decoupling capacitors near the via’s. Robert Feranec has made a youtube video about this peculiar topic.
This is my layer stackup:-
1st layer - GND and signal:
Track width - 0.5mm
There are so signal traces in the 2nd and 3rd layer. But signal traces run on both layers(1st and 4th) through vias. So, should i be concerned about any length tuning or anything?
Another question: can any problems arise from the 3 GND planes? Can it interfere with the oscillator(Y1)?
Thanks for helping!
That is a very bad layer stackup, for the reason I mentioned earlier. Any signal that goes from the front layer to the back layer changes it’s reference layer from GND to +5V. A much more common layer stackup is to use both inner layers for GND (because prepreg is much thinner then the core) and then route power as tracks. On a PCB as simple as this it does not matter much, but when your designs become bigger and more complicated, this becomes much more important.
If you are serious about signal integrity, then go watch the 2h and 19 minute video from Rick Hartley about how to design a GND plane. Aditionally, Robert Feranec has made some nice video’s about the pro’s and con’s of different layer stackups, combined with emulations from field solvers to show how different constructs influence the layout quality and signal integrity.
Can the top layer be PWR plane with a high clearance (>1mm)? Will this help? If this is ok to do, i can get rid of the 2 inside layers and just create a 2 layered PCB.
Is signal integrity something to be worried about with a simple circuit like above since it uses SPI and UART?
I solved the pad design issue with a keepout zone. I will keep this also in mind next time.
Thanks
As I wrote earlier:
If you have a good GND plane, and properly placed decoupling capacitors, then the rest of the power can be routed as (high current) tracks.
Also get some practice by modifying pad properties. A keepout zone works, you have added a few extra vertices to the GND plane and route it around that pad. And there are probably other options too, but modifying pad properties is probably the simplest.
For signal integrity and EMC, it’s not whether you use SPI or UART, but the steepness of the flanks. It’s how fast a signal goes from zero to one. (and later from one to zero). For a small PCB with short tracks it does not matter much. There is also a very big difference between a hobby PCB that “just has to work” and a commercial design that has to go through formal EMC testing (which is quite expensive, so you really want to get it right the first time).
For a proper design, you should also consider filtering (series resistors, chokes, full PI filters) for any signals that leave the PCB (or are not directly referenced to the GND plane). ESD is also a concern for anything leaving the PCB and accessible to the hostile outside world. ESD protection inside IC’s is designed to be good enough to prevent damage during manufacturing, but not much beyond that.
My strategy for 2 layer PCBs is to go with VCC under microcontroller and connect from there to all its VCC pads and distribute VCC form there through its corners and VCC pads to other ICs. That way I avoid VCC tracks going around uC and making it difficult to connect signal tracks. If I really have to cross VCC with signal tracks I use 0R to avoid any break in GND plane.
In past I have posted my 2 layer example here:
All vias you see are GND.
Top right of uC there is 0R jumping over 3 signal tracks and bottom right one jumping over 2 signal tracks.
