I’m worfking on my first PCD. The is an audio classD amplifier. I have a small issue with the copper fill of the ground plane: there are 2 pins GND pins of the main chip that do not connect to the GND plane. Others are.
The rat nest shows that the connection is missing, so the different elements seem to bvelong to the same net.
I tried to add a manual copper filled zone, but it does not work either.
Help warmly welcomed
files are in https://www.dropbox.com/sh/q9yqaaj2uphw94p/AADJNs0UO2E5k052swV6g77Xa?dl=0
The 2 GND pins are not connected because of the “Thermal Clearance” settings of the zone. In your drawing it is set to the default of .508mm.
If I reduce this value to 0.35mm it looks like:
You can edit this by clicking on the edge of a zone or hovering over the edge and then press “e” for edit.
This will change this setting for the whole net.
Note that C11 has also gotten an extra thermal relief spoke.
You can also select a pad and press “e” to edit the settings for only that pad.
In this 2nd screenshot I set the thermal relief option for the bottom GND pad to “Solid” and regenerated the zone with “b”. You can now see much clearer the effect of the thermal relief of the top pad. the thermal reliefs of the GND pads were masking each other.
Another small thing:
The Left via of SPK_OUTB+ is 5 via’s stacked on each other, you may want to delete 4 of those
Thanks a lot Paulvdh for the detailed explanations and solutions how to solve my issue.
I played with the settings to better understand the different options. Problem solved.
However, I didn’t spotted the 5 stacked vias. On which plane is it ? F.Cu or B.Cu ? How do you spot this type of thing ?
Efcis’ tip of using > Pcbnew / Edit / Cleanup Tracks and Vias …
works better than my suggestion .
you hover over a via and press “m” for move.
And then KiCad ask which of the 5 via’s you want to move.
See the screenshot for the location:
With other via’s KiCad only finds one and it simply selects that via to move it.
It does not matter which layer is selected, as the via’s go through the board. Via’s even get selected if the current active layer is a non-copper layer.
It would be nice if KiCad’s DRC could detect accidental double via’s with the same coordinates. DRC does detect if the holes overlap in “binocular” fashion". This would make the PCB unmanufacturable, because the drills would break. But for some reason it ignores multiple via’s at the same location. For production it also would not be a disaster, just the drill moving up and down a few times in the already drilled hole.
An easy way to check for double via’s is probably to generate the excellon drill file, and then sort the coordinates with a text editor or a spreadsheet.
You can also use “Edit / Cleanup tracks and vias” to remove redundant vias (and clean tracks, if needed).
Thanks all for the help. It’s muche better now
jmf11 - another way to look at this issue is that the fill has created an “island” which is not able to be connected to the main fill. With a little experimentation, you can often add a trace that connects the “island” to the “mainland”. Start placing a trace on the island, then add a Via and go to the mainland, place another Via. That should connect the two.
This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.