Global Pad to Track or Mask to Track clearance?

My fab constraints have 4-mil clearance requirements for both copper-to-mask and mask-to-copper. This results in a requirement of 8 mils from pad to track (4 mil pad to mask edge, 4 mil mask edge to track). I’ve figured out I can accomplish this by setting the local clearance rules on every single component to have an 8 mil pad clearance, but was hoping maybe there’s a global setting somewhere? Failing that, what would it take to automate setting the pad clearance for all components on a board?

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Item to item rules aren’t possible in v5.1, but the unstable development version 5.99 (nightly builds) has a new DRC system with a text based rule language with which it should be possible to set rules between certain kinds of items.

I do not understand your requirements.
From the little I know, copper to mask clearance is only for pads, and not for tracks. On top of that, Solder mask also needs a minimum width to be printable between pads.

Normally pads inherit the clearance rules from the net, but they can be overruled by setting them for the pad individually or for a whole footprint, but you apparently already know that.
Have you thought about copying footprints to a personal library, then setting the clearance for those footprints in that library and use those for your project?

I think that KiCad V5.1 does not even have a check for Mask to track clearance. This probably is one of the underdeveloped parts of KiCad. Most common practice that I know is to set the solder mask clearance to zero, and then let the fab decide what they do with solder mask expansion.
There is a global setting related to this: Pcbnew / File / Board Setup / Design Rules / Solder Mask/Paste

Sounds like I should try the nightlies, but to attempt to clarify:

  1. Minimum trace/space are both 4 mils (so “track width” and “clearance” are both 4 mils)
  2. Solder mask must be expanded by 4 mils relative to pads (“solder mask clearance” = 4 mils)
  3. Masked copper must be 4 mills from the mask edge. This is what I’m looking for a better approach for.

2+3 result in a minimum pad-to-track of 8 mils.

In Eagle I can achieve this by setting pad-to-trace and pad-to-via constraints of 8 mils. In KiCad I’ve figured out that the same thing can be accomplished by setting the “Pad clearance” to 8 mils, but I have to do that on every single footprint. Was looking for an equivalent global setting or script that could automate it.

I partly take back what I said. The new DRC engine handles items only in the same layer, not between for example mask and copper layer.

The new DRC engine handles items only in the same layer

That’s fine, if I can use it to set set pad-to-track and pad-to-via clearances that are larger than the track-to-track clearance.

There is also such a thing as: solder mask defined pad

The idea is that copper pads are bigger then the cutout in the solder mask, and if their relative position changes the amount of exposed copper stays the same.
When you do that, then solder mask cutouts are always smaller then pads and there are no extra rules.

I do not know much about the (dis) advantages of this, so can’t help there.

Sure, but that would require I make new footprints for everything, requires awareness of when components will require ganged apertures to switch to a conventional pad.

I’ll grab the nightly later today and see if I can set up constraints the way I want. Also hoping that this will allow clearance matrix style rules between net classes.

Development of new features (and hopefully introducing new bugs) in kicad-nightly V5.99 is pretty much frozen, and for already quite some time all effort is going into making it ready for release. There is hope of KiCad V6-rc1 being released by the end of April, and an official KiCad V6 somewhere between a few months or half a year later.
Response to bug reports is excellent. I’ve reported 10+ bugs, and if it’s easy to fix, it’s usually done within a day. record is 34minutes between report on gitlab and a comited to git. More complicated stuff takes longer.

As far as I know there is no manual for the rules based DRC yet. There is a lot of info in this long thread:

But do you really need to compensate the solder mask. Of course you must layout the copper such that it is possible to make the mask: 8 mil pad to track (and copper pour); for pad to pad you need the 8 mil + whatever the min web is your fabricator can do. But if your copper is OK, doesn’t your fabricator accept a mask with zero ring? Compensating mask is a basic function for CAM software. Do you really need to go to all that pain.

But do you really need to compensate the solder mask.

Yes. From what I can tell, their DRC complains (requiring a human review to go to fab) if:

  • there is mask within 4 mils of any copper flash that has an overlapping paste flash, or
  • there is copper within 4 mils of a mask boundary (on either side) that is not connected to the closest unmasked copper flash (guessing slightly at how exactly this test is implemented, but it’s remarkably strict, complaining even about traces connected to other pads in the same mask gang if they cross near the mask gang elsewhere).

I’m guessing these constraints arise from fairly sloppy (presumably jetted, not metal mask based) paste application.

As I’ve said, I these are trivial to comply with in Eagle by setting the “different net” pad-to-trace and pad-to-via clearance to 8mil but in KiCad I can only approximate it by setting the pad clearance to 8mil on a per-footprint basis (which generates spurious pad-to-pad errors on 0201s and most ≤0.5mm pitch parts).

I’m working right now on getting the nightly installed to see if the expression-based DRC allows describing this constraint.

I do not agree with this.
I find it a very sensible check, and are more sort of surprized this is not more common to check.

It has nothing to do with:

The job of solder mask is cover copper that should not be soldered. With mechanical stuff there are always tolerances, and 4 mil is a common tolerance for PCB production. Meaning that if the distance to some solder mask cutout and unrelated copper is less than this tolerance, there is a possibility that the other copper part could get exposed if tolerances line up badly.

And of course this is exposed unrelated copper on places on / near pads where paste is applied, so the risk of making shorts is real.

Therefore, instead of finding this “remarkably strict”, I’d rather think this is worth a feature request for KiCad on gitlab.

To clarify, I meant the DRC rule was very well implemented (not producing false positives, but catching even marginal violations) not that the PCB constraint was unreasonable.

I agree with paulvdh, the mask clearance to these pads is needed.
But I still wonder whether you need to adjust the mask yourself. You write that otherwise the fabricator must perform a manual check on the data. But all fabricators manually check all jobs before fabrication. There simply to many jobs with really crappy data, painted pads, sloppy outlines etc. It is more than DRC errors. And you do not know in advance how good the data as. All jobs are manually checked.
Does he reject the job if you send it without mask clearance?
(You must tell him somehow which SMD rows he may gang open, and doing that yourself is a way. I am not aware of any standard for this.)
If he has such good DRC’s surely doing the mask adjustment is a piece of cake for him.
Can you share who that fabricator is? I would like to have a look at his website.

Can’t share the service right now (invite-only alpha) but they claim to be 100% automated and without human involvement (on their part, the underlying fab house obviously requires humans) until the assembly stage (tape loading, pick&place origin/orientation programming, and final depanelization).

Their current setup for the mask ganging is that you need to do it yourself. They DRC-fail webs or fingers under 4 mils. I’ve been drawing rectangles over pad groups or making special footprints.

The mask adjustment isn’t the problem - it’s the different copper clearance requirements for pads. Unless they change their fab-level mask spec, there will still need to be 8 mils from pad copper to trace/via copper to accommodate mask positional error and offset.

(Also kinda uncool to needlessly assign gender to a service. Plural pronouns work just fine.)

Indeed, the DRC in any CAD system should have a convenient way to check pad-to-pad, pad-to-track/pour, copper to copper clearances, each with their own value. And it does not need to bother about the mask, once the copper is OK the fabricators can tweak the mask to their desire. (Note the plural, I am learning. I will come back to my unintended uncoolness in a separate reply, it is a separate topic.) Mask ganging yourself is a convenient way to indicate it is allowed, but there is no need to respect a clearance for that.

I am intrigued by the alleged hands-off service of your fabricator. There are so many things that can be and all too often are wrong in fabrication data. All too often the pads are not even flash, but painted, or represented by outlines, as copper pours - this was the case in KiCad until recently for all but the simplest shapes. So how does the fabricator even know where the pads are then? How does the fabricator knows which electrical test to perform - or maybe he doesn’t. I understand you cannot share the name, but maybe you can share what the data requirments are (I skillfully avoided ‘his data requirements’) and what the fabricator guarantees, e.g. does he perform an electrical test? Please share what you can share.

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I apologize for my uncoolness. I am not a native English speaker, and sensitivities are not easy in another language. It is further complicated by the following. In my mother tongue words have a syntactic gender. This has nothing to do with anything, there is no rhyme nor reason. Company is neutral, enterprise is female, and fabricator is male. So in my native tongue, ‘the fabricator… he has automated data input’ is required syntax, as is ‘the enterprise… she has a global presence’. A useless complication, but it is how it is.
So when talking about a fabricator in English, ‘he does this or that’ comes naturally to me, even if it is uncool. But what is the cool thing to do? Your trick of using plural does not always work. Suppose I refer to your specific fabricator? It performs electrical test feels disrespectful. He/she performs electrical test is clumsy, and not correct, I am not talking about a person. What is the cool way to write this?

‘They’ is a perfectly acceptable form in this context. It can be used as a collective term for an organisation, team or an entity.

'Cheapo boards' are a new fabricator. They will run an electrical test on your board.

Anyhow, your English is rather better than any of the other languages that I can claim any degree of fluency in :slight_smile:

True. Plural works here too. Thanks.
Fortunately, in English the plural is gender neutral. (And so it is in my language,)
In Latin, I believe, ‘they’ is gendered, a male-they, female-they, and neutral-they. One wonders what the Romans had to write to be cool.

(responding to the vaguely on-topic comments above, wasn’t trying to derail things that much)

There are so many things that can be and all too often are wrong in fabrication data.

Indeed. Their approach is basically “it’s your problem” – they push all the work onto you. Because of this their checkers can be exceptionally picky. It took me a couple tries and some emails back and forth to figure out how to get their tool to accept my footprint and package spec for the MPM3610. It required making four overlapping pads for each of the big pads at the bottom which their tool detected as 3 normal numbered pads and a thermal pad. They’ve since added a system to mark pins as shorted on the component which I think would make this far easier.

Their netlist-from-gerber logic for the DRC seems to be fairly pedantic. I’ve had trouble where I drew a single track in Pcbnew straight through several in-line pins that were all connected. Pcbnew’s DRC was fine with it but the online tool flagged it as an issue and I had to go back and draw short tracks between each of the pads.

I suspect the presence of paste is more involved in their definition of “pad” than I had previously suggested. I can think of a couple of ways of fairly reliably defining a pad by considering the copper, paste, and mask together, but flashes were definitely involved in how they did at at the time of the MPM3610 footprint issue.

maybe you can share what the data requirments are

Off the top of my head: Gerbers for copper, paste, mask, and legend. NC drill file. CSV Placement files with distributor part numbers. Uploads of datasheets not on file with distributors. Web-based isolation of package drawings within datasheets. Web-based specification of package/pin geometry. Alignment of package placement to the rendered gerbers and identification of a datum pin. A few days after ordering you identify datum pins and datum pin markings on photos of the parts and confirm alignment to the package specs.

what the fabricator guarantees, e.g. do they perform an electrical test?

I think that’s something they’re trying to figure out. I assume they’re having the fab do flying-probe testing of the boards (based on the netlist extracted from the DRC pass presumably), and they’ve mentioned acquiring an x-ray machine for post-assembly inspection. They only thing I remember them calling out is that MSL 5 or higher parts are explicitly best-effort.