Giant grey dot in schematic view

Hi all.
After several months, I went again to Kicad to check some old PCB before to etch them.
Honestly I don’t remember well, but allegedly before…to drop Kicad last time I updated the version (currently my version is 5.1.2 (Win 7/64)).
Well, as I open a project and load a schematic, I get a popup in order to remap the symbols, quoting a non compatibility with previous versions once remapped.
Ok, no matter, I do it.
When the schematic opens (with no changes, as I can remember), I notice a grey background and no frame with the schematic info anymore… Zooming out, I realized a giant grey dot sorrounding my schematic…
I tried to eliminate the grey through the settings menu (background, etc), but no way.
screenshot.2

There is any reason for that giant grey dot and how to fix it?

Thanks

Andrea

No idea what it is. Can you attach the schematic file here?

Sure.
Here you go.
Datalink.sch (37.8 KB)
For the sake of clarity, I use some custom symbols (It’s easier to me)

I could not reproduce that, but I do not have your symbols either:

Application: Eeschema
Version: (5.1.6)-1, release build
Libraries:
    wxWidgets 3.0.4
    libcurl/7.66.0 OpenSSL/1.1.1d (Schannel) zlib/1.2.11 brotli/1.0.7 libidn2/2.2.0 libpsl/0.21.0 (+libidn2/2.1.1) nghttp2/1.39.2
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
    wxWidgets: 3.0.4 (wchar_t,wx containers,compatible with 2.8)
    Boost: 1.71.0
    OpenCASCADE Community Edition: 6.9.1
    Curl: 7.66.0
    Compiler: GCC 9.2.0 with C++ ABI 1013

Build settings:
    USE_WX_GRAPHICS_CONTEXT=OFF
    USE_WX_OVERLAY=OFF
    KICAD_SCRIPTING=ON
    KICAD_SCRIPTING_MODULES=ON
    KICAD_SCRIPTING_PYTHON3=OFF
    KICAD_SCRIPTING_WXPYTHON=ON
    KICAD_SCRIPTING_WXPYTHON_PHOENIX=OFF
    KICAD_SCRIPTING_ACTION_MENU=ON
    BUILD_GITHUB_PLUGIN=ON
    KICAD_USE_OCE=ON
    KICAD_USE_OCC=OFF
    KICAD_SPICE=ON

You should attach Datalink-cache.lib at least. Better with Datalink.pro.

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Incoming files…

Datalink.pro (837 Bytes) Datalink-cache.lib (6.2 KB)

Possibly you could have a corrupted page layout file or need to set location of the file.

Still not able to reproduce it.

Do you know which frame are you using ?

EDIT:
I’m thinking exactly what @mendy commented while I was typing.

I am on 5.1.6 forgot to mention. der.ule looks same on my system with symbols and no wires.

Uhmmmm…
Now I have to go working, but tomorrow I’ll have a look to your suggestions and let you know.

Same v5.1.6 here. There are no wires but local labels.
No sign of the grey artifact. There are 18 components and 18 components in cvpcb too.

Mendy was right…
I made a new layout file and evrything was fixed.
Thank you very much

Andrea

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