I have a small board i’d like to send to JLC PCB for manufacture.
To take the most advantage of the 100mm x 100mm space i’d like to tile the design so as it’s manufactured with scores in it and i can snap off the pieces as required.
I have previously attempted this in KiCad and it kind of worked, but all my ground connections to the flood were lost. I think the simple cut and paste i tried to do broke things.
The boards were scored nicely however, and clearly the edge cuts through the inside of the design worked fine per the JLC suggestion they would be taken as score lines.
So i think i need a gerber editor or a script to generate a tiled gerber file.
Anyone have any experience or suggestions they could share?
Is panelization ourselves likely to incur additional charges on top of the $2 JLC PCB Prototyping service?
If not then full panelization is perfect.
Unfortunately I’m on Windows so i suspect the learning curve is going to be steeper, and the need to install KiCad an additional time is a little annoying, but can’t hold that against an open source project.
Will see how i go and report back.