Generate netlist

Suppose I have standard cells .libs information, using this info I need to generate verilog netlist with dummy connections. Can anyone please help me to provide a script to do above work. I only need a short script to get netlist from .lib file for idea purpose in PYTHON language. later I will modify that script upon my need.

I am not sure what you try to do here. Do you use KiCads eeschema for chip design or digital simulation or did you possibly post this on a wrong forum (This is the forum specifically for the open source printed circuit design tool KiCad).

Not clear on what you want but, if simply wanting to

Simple approach: the Lib file from Kicad is just a Text file that any Text editor can open. Thus, coding a script is simple - you can parse and do what you want with the data… Thus, I imagine your ‘Cells .lib’ is a Text file and can go from there…

I’m guessing here, but maybe the “skidl” project is useful to you.

One of the goals for skidl is to generate a KiCad netlist from Python code.
It is especially useful for repetitive schematics.
Take a big multiplexed display as an example. With skidl it is a few nested loops that generate the connections.

With the search below for the “studio clock” you find an example project generated with skidl.