General layout question: MOSFET footprint such as 2x2 PQFN

I have been doing power for many years…but I have a question concerning some semiconductor footprints. In this datasheet drawing for ON FDMA86551L, pins 1,2,5,6 and the large belly pad in between are all connected to the MOSFET drain. Pin 4 and the smaller belly pad are both connected to the source. What is the reason for separating the drain pins from each other (and the source pins from each other) in the device and the pcb footprint?

I am pretty sure that I could merge the common pads to make a 3 pad footprint that would work for hand assembly. The result would look more like a small D-pak with a fat source pin (#2). But what is the reason for not doing that everywhere? Is it self-positioning of the device during reflow soldering?


I would guess it’s something like that. Also covering large areas with solder (melted paste) so that it’s evenly spread without problems is notoriously difficult. Maybe the result is better guaranteed with several smaller pads.

Often internal device bond wires dictate pin configuration. High current means more bond wires and pads in parallel.

I suspect that the die is directly soldered to the centre pad and that the other drain pads are connected by the lead frame
Source bond wires are going to be the current limitation

Thanks, everyone.

It sounds like everyone is where I am; basically thinking based upon soldering process and the internal device construction. Unfortunately I don’t get to do my own KiCad layout, but I will be directing a pcb designer who will use Altium. I think I need to check with the pcb assembly house to see whether my 3-pad design can work OK or whether they want to use something closer to that shown on the datasheet. I would like to be able to swap FETs in the lab if I need to but most important is that I do not make difficulty for the assembly house.

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