Although I’ve used KiCAD for a few years, I have found a number of ongoing quirks to be costing a lot of time needlessly in manual error checking. I’ll put these in list form:
- MOSFETs use GDS notation in both the eeSchema library components and in the PCBNEW footprint pin names, but NPN/PNP transistors use numerical pin names in both. Why not BEC notation in both? This means one more quirk I have to account for.
- NPN/PNP transistors all have a Y-shaped pin offset and are rotated 45 degrees. I made a simple 3-in-line for parts like the BC457 NPN single diode (http://media.digikey.com/Renders/~~Pkg.Case%20or%20Series/TO-92-3(StandardBody),TO-226_straightlead.jpg). Shouldn’t the footprint be aligned according to the major features of the body of the component rather than pin orientation?
- Polarized capacitors follow the traditional notation, in terms of their footprints, that the anode (positive terminal) is square, and the cathode is circular. However, for diodes (PN, Schottky, and Zener), this is the opposite (https://learn.sparkfun.com/tutorials/polarity/diode-and-led-polarity). The silkscreen image is correct, and the stripe/band is closest to the cathode, but the cathode has a square pad, and the anode has a round pad. This really irks the design companies I use, as it can result in the person assembling the board potentially installing diodes backwards if I have a reference designator overlapping the diode band symbol on the silkscreen.
- Within eeSchema, is there a way to just turn on, globally “show all pin numbers and names”? If I manually edit a specific library module, I can temporarily turn on pin numbering, but it goes away when reloading the schematic, since I’m not able to overwrite the standard libraries that ship with KiCad (and rightfully so). I found myself needing this when accidentally using a capacitor symbol in place of a polarized capacitor symbol, and wanted to make sure I didn’t accidentally flip or rotate the component.
- When back-importing footprint names into eeSchema after completing the symbol/footprint mapping in CvPCB, the net names are forcibly rendered, and the only easy way to disable this globally was via this StackExchange post (http://electronics.stackexchange.com/questions/57725/footprint-field-visibility-options-in-eeschema-kicad), which involved basically executing a regex replace query on the netlist while open in a text editor.
:%s/^F 2\(.*\)0000 C CNN$/F 2\10001 C CNN/
. While I’m comfortable working with VIM, GREP, SED, etc, I don’t think this sort of thing will attract less technical PCB designers (ie: Windows developers who have had less exposure to binutils on *NIX systems). - “Update component in library”: When I use this option in PCBnew, it not only adjusts the pin names, locations, graphics, etc, it also sets the “Net Name” which has disastrous effects when I update all components in the PCB layout and start actually routing tracks. Should this effect be taking place?
I know this just seems like a grocery list of gripes, but I am actually interested in contributing to development and updating the libraries. My concern is, are these above woes/gripes by design (ie: intentional), or are they seen as “legacy features” (ie: bugs that have been around so long it would cause even more harm to fix them), or some other reason that eludes me?
This is a great tool, especially considering that it’s FOSS, something I strongly support. I would like to see it continue to improve, and am willing to work to that end if these sorts of issues are allowed change.
Thanks!