I’m repeatedly getting the above error message and believe I have been through all the posts from community members with suggestions of help but to no avail.
My pcb has 24 plated through holes, (a custom library item), situated around an ESP-32 development board to allow me to either probe one of the GPIOs or link it to somewhere should the necessity arise, yet only 3 of these actually flag the error. I have tried changing the footprint to one from the Kicad library but get the same 3 errors
Since I only get this with 3 out of 24 identical points, could this be a bug?
Show us the PCB region with reported problem.
The best would be to zip your project and include in your post. Someone will probably look at such project to find source of problems.
OK, so if your solder mask for your pad/hole is quite a bit bigger than your pad it is very possible to have pads sufficiently far apart from each other such that they do not fall foul of DRC checks on copper clearance but could then fall foul of overlapping solder mask and the error you are seeing.