FPGA Autogeneration

One general question: There are special file formats for FPGAs, provided by their manufacturers, that OrCAD or Altium understand, enabling automatic generation of multipart symbols for these FPGAs. Does KiCAD offer anything similar?

We would love to support that. If you have either a specification document or example files with expected output, it would be great to add them to an issue on GitLab. This is the sort of feature that many people would like to support but I think that we are just not aware of it.

I did something like that with kipart. I generated part libraries for GOWIN, Lattice and Xilinx FPGAs from their zipped CSV files using specialized *_reader.py files in combination with kipart.


Boundary scan description language (BSDL) is a standard format used for JTAG testing in PCB manufacturing. It describes the internal component structure for testing, Pin Definitions and Net names are all included. Example File

I appreciate the responses. Please note that the forum is not set up for tracking information. We’re not implementing this until at least v9, so it needs an issue or it will be harder to find the relevant info

Does the BSDL specify which unit within the FPGA each pin is assigned to? That would be necessary in order to create the units for the FPGA part symbol. I looked into an 1149.6 BSDL file for an Intel FPGA and it didn’t appear to have this information, but maybe it’s encoded in some way I didn’t notice.

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