I’m designing a two layer board with a power inductor for a DC-DC converter. I want to avoid tracks running below the inductor.
What is the better method, a or b ?
a) copper free area below the power inductor
b) copper area without any connection to surrounding on both layers
If you want to avoid tracks under the the inductor it seems that the best option is a). Some kicad SMT inductor footprints have already defined a keepout zone between SMT inductor pads.
Shielded inductors I use have pads extended under the inductors. I am using top layer copper free area but not under whole inductor, but under half+ of inductor around its switching pad. My idea is to minimize the capacitance to be reloaded with each pulse. At bottom I have full GND zone that I treat as shielding. I assume that distance to bottom is higher so capacitance clearly smaller.
But all of it is based only on my imagination and not being DCDC educated designer.
I highly doubt you want an unconnected copper area under an inductor. If you decide to keep it completely copper-free, use a keepout zone. Of course, you could also use a Keepout to prevent tracks but allow pours.
This Si Journal article by Kenn Whatt details ground planes under inductors (and switching elements) of an SMPS. Its focus is the EMI implications.
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