I have a couple of questions (or rather, one question and one request for comments/feedback) regarding this simple (but I think useful) idea I thought of last night. Decoupling capacitors are typically a pain in that they’re abundant, and they end up taking up a lot of time in tedious and repetitive tasks (especially in digital designs, with microcontrollers, SoC’s, DSPs, etc.).
I had already created a schematic symbol C_X7R_402, which has the footprint, and also Digikey part number, to save the time when dealing with the BOM and component selection).
Last night, it occurred to me that the layout is actually the more painful part (in the schematic, one can always specify those parameters for the first, and then copy-n-paste whenever I need additional decoupling caps). We need to place the capacitor, and then draw thick traces that go from the cap to the vias to ground and power planes. That is, assuming the somewhat-typical topology as shown in this figure below:
I created the following footprint (using the C_0402 KiCAD footprint as a starting point), placing through-hole pads without mask (so that they are effectively vias — the following is preliminary, you may use it, but at 100%-your-own-risk, no guarantees or warranty whatsoever, etc. etc.):
(module C_decoupling_402 (layer F.Cu) (tedit 5D65160F)
(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags capacitor)
(attr smd)
(fp_text reference REF** (at 0 0.9) (layer F.SilkS)
(effects (font (size 0.6 0.6) (thickness 0.12)))
)
(fp_text value C_decoupling_402 (at 0 1.17) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
(fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
(fp_line (start -0.93 0.47) (end -0.93 -1.12) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.93 -1.12) (end 0.93 -1.12) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.93 -1.12) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.25 0.25) (thickness 0.04)))
)
(pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
(pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
(pad 1 thru_hole circle (at -0.485 -0.7 90) (size 0.63 0.63) (drill 0.3) (layers *.Cu))
(pad 2 thru_hole circle (at 0.485 -0.7) (size 0.63 0.63) (drill 0.3) (layers *.Cu))
(pad 1 smd rect (at -0.485 -0.35) (size 0.59 0.7) (layers F.Cu))
(pad 2 smd rect (at 0.485 -0.35) (size 0.59 0.7) (layers F.Cu))
(model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
One little problem. This is what it looks like:
Functionally, there’s no problem at all — it’s more the “eyesore” aspect. I’m referring to the triple labeling (well, triple × 2, since each element shows the pin number and then the net name — GNDD and +3.3V). The two capacitor pads should show them, and I think it is ok that the vias also show them. I can’t find a way to hide the labels in the middle pad (the one playing the role of the trace connecting the capacitor pad to the via). Is it possible?
Notice that the vias’ locations depend on the orientation of the GND/Vcc pins that this will connect to, but one footprint suffices: we get the four combinations through rotating the footprint (two possibilities) and swapping the connections in the schematic (two possibilities). I will, however, create an additional footprint where the vias are aligned with the capacitor (i.e., instead of to the left of the capacitor pads, they will be above and below).
Aside from the “eyesore detail” mentioned above, any other comments/feedback on the idea or the implementation? (is this something that’s been already done and available somewhere out there?)
One minor (maybe moderate?) inconvenience is that the orientation of the capacitor in the schematic has to be consistent with the layout. I guess I could solve that with the custom schematic symbol for decoupling caps (putting marks on the side, showing where the vias will be located)
