Footprints for decoupling capacitors


I have a couple of questions (or rather, one question and one request for comments/feedback) regarding this simple (but I think useful) idea I thought of last night. Decoupling capacitors are typically a pain in that they’re abundant, and they end up taking up a lot of time in tedious and repetitive tasks (especially in digital designs, with microcontrollers, SoC’s, DSPs, etc.).

I had already created a schematic symbol C_X7R_402, which has the footprint, and also Digikey part number, to save the time when dealing with the BOM and component selection).

Last night, it occurred to me that the layout is actually the more painful part (in the schematic, one can always specify those parameters for the first, and then copy-n-paste whenever I need additional decoupling caps). We need to place the capacitor, and then draw thick traces that go from the cap to the vias to ground and power planes. That is, assuming the somewhat-typical topology as shown in this figure below:


I created the following footprint (using the C_0402 KiCAD footprint as a starting point), placing through-hole pads without mask (so that they are effectively vias — the following is preliminary, you may use it, but at 100%-your-own-risk, no guarantees or warranty whatsoever, etc. etc.):

(module C_decoupling_402 (layer F.Cu) (tedit 5D65160F)
  (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source:, generated with kicad-footprint-generator")
  (tags capacitor)
  (attr smd)
  (fp_text reference REF** (at 0 0.9) (layer F.SilkS)
    (effects (font (size 0.6 0.6) (thickness 0.12)))
  (fp_text value C_decoupling_402 (at 0 1.17) (layer F.Fab)
    (effects (font (size 1 1) (thickness 0.15)))
  (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
  (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
  (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
  (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
  (fp_line (start -0.93 0.47) (end -0.93 -1.12) (layer F.CrtYd) (width 0.05))
  (fp_line (start -0.93 -1.12) (end 0.93 -1.12) (layer F.CrtYd) (width 0.05))
  (fp_line (start 0.93 -1.12) (end 0.93 0.47) (layer F.CrtYd) (width 0.05))
  (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer F.CrtYd) (width 0.05))
  (fp_text user %R (at 0 0) (layer F.Fab)
    (effects (font (size 0.25 0.25) (thickness 0.04)))
  (pad 1 smd roundrect (at -0.485 0) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
  (pad 2 smd roundrect (at 0.485 0) (size 0.59 0.64) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
  (pad 1 thru_hole circle (at -0.485 -0.7 90) (size 0.63 0.63) (drill 0.3) (layers *.Cu))
  (pad 2 thru_hole circle (at 0.485 -0.7) (size 0.63 0.63) (drill 0.3) (layers *.Cu))
  (pad 1 smd rect (at -0.485 -0.35) (size 0.59 0.7) (layers F.Cu))
  (pad 2 smd rect (at 0.485 -0.35) (size 0.59 0.7) (layers F.Cu))
  (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
    (at (xyz 0 0 0))
    (scale (xyz 1 1 1))
    (rotate (xyz 0 0 0))

One little problem. This is what it looks like:

Functionally, there’s no problem at all — it’s more the “eyesore” aspect. I’m referring to the triple labeling (well, triple × 2, since each element shows the pin number and then the net name — GNDD and +3.3V). The two capacitor pads should show them, and I think it is ok that the vias also show them. I can’t find a way to hide the labels in the middle pad (the one playing the role of the trace connecting the capacitor pad to the via). Is it possible?

Notice that the vias’ locations depend on the orientation of the GND/Vcc pins that this will connect to, but one footprint suffices: we get the four combinations through rotating the footprint (two possibilities) and swapping the connections in the schematic (two possibilities). I will, however, create an additional footprint where the vias are aligned with the capacitor (i.e., instead of to the left of the capacitor pads, they will be above and below).

Aside from the “eyesore detail” mentioned above, any other comments/feedback on the idea or the implementation? (is this something that’s been already done and available somewhere out there?)

One minor (maybe moderate?) inconvenience is that the orientation of the capacitor in the schematic has to be consistent with the layout. I guess I could solve that with the custom schematic symbol for decoupling caps (putting marks on the side, showing where the vias will be located)


For your colorscheme, is the tan your soldermask? I ask just to make sure you are making sure that there is at very least a dam of mask between your capacitor pads and the via’s hole to avoid the through hole from robbing paste during reflow. Are you planning on tenting the vias with mask?


I think I understand what you’re asking, and I think my design is ok. If by “tan” you mean the 255/222/184 (that’s the RED/GREEN/BLUE values), then yes, that’s the mask. The yellow is the ground plane (an inner layer), and the red/maroon-ish is of course the top layer.

Just to make sure we’re in sync, this is the 3D rendering of that part of the board:

I essentially reproduced what I normally do manually (placing the capacitor, connecting with traces to a via). On the bottom/back side of the board, the “vias” are also covered.

Does it look ok with respect to the details you pointed out?


Yep. I was just confirming. Looks good to my untrained eye.


Isn’t there a risk with reflow soldering due to thermal energy going easily from you pad to the vias and causing a bad solder joint ?


No. ------------------


To expand a bit on eelik’s reply: no, that’s one of the interesting aspects with reflow soldering; you heat up everything equally (ideally, all at equal temperature — in practice, well, it should be very close to that, unless the oven has leaks, or it’s an extremely poor quality unit, or you raise temperature too fast).

Keeping in mind the “equivalent electric circuit” of a thermal system: temperature corresponds with voltage, heat (flow) corresponds to current. Since we have all parts of the board at the same temperature, it is like having all points in a circuit at the same voltage: all currents will be zero. (we add the assumption that temperature is changing slowly, so the effect of the “capacitance” of elements with mass that can accumulate thermal energy and cause some dynamics is negligible).


Let’s take a THT component and manual soldering with iron (which actually could be a problem without thermal spokes). You have e.g. 4 x 0.25 thermal spokes connected to a zone, possibly on the other side, too, and a thick metal wire. You could add quite many vias for one SMD capacitor to reach the same heat dissipation effect. Usually more than one via for one pad is recommended in case of bypass capacitors.


Is this a comment in response to my original message? If so, are you suggesting that the footprint should have more than one via per capacitor pad?

I know that that is a good idea, to reduce the trace inductance. But I think that’s not a good idea for the footprint, given the possibility of additional layout constraints — or, I guess I could have three different footprints, and the user selects the right one given the layout constraints: one with two vias like the one I posted; one with two vias along the long axis of the capacitor, and one with two vias per capacitor pad (essentially, the “superposition” of the former two, as it were).

Did I understand correctly, and does my suggestion/interpretation make sense?


Sorry for unclearness - I continued Sims-me-you subthread.


Just something from the original post:

No need to make more different symbols for different body size or temperature-dependent capacitors. I use two capacitor symbols: one for non-polarised “C” and one for a polarized “CP”. Footprint is left empty when defining symbols, so footprints should be filled in later for actual case size.


Some people prefer the fully specified workflow. Learn to accept that.


@Rene_Poschl I didn’t want to be offensive.
I’ve seen PCB design with separate symbols even for different resistor values (ha had lots of “R4k7”, “R2k2”, “R1k” etc. kinda symbols)

As we are engineers looking for optimal solutions, creating C_X7R_0402, C_X7R_0603, C_X7R_0805, C_X5R_0402, C_X5R_0603… seems a non-optimal way for me.
I simply tried to help cal-linux with my post; I don’t really force him/her. It’s a free world (more-or-less:)))


Flexibility of KiCad is a strength, but after placing hundreds of resistors which all are inevitably 0402 I have learned that not using a symbol which has the footprint predefined is suboptimal.


I think you might be wrong!

Are you 100% certain that you can purchase that part in that package?


At some point in time you need to decide which exact part to buy. In the fully specified workflow this is done at the moment of selecting the symbol. You select the symbol that fits the part you selected. This symbol already defines the correct footprint for it and the required BOM information.

The generic workflow postpones this decision until some later point. You select the footprint to fit the part you finally select plus need to at this point add BOM information to the schematic as well.

As with many things a well rounded mixture of both makes more sense than strictly following either of the two workflows. I personally for example do not have overly specified symbols for capacitors, resistors, … but have only one per footprint. (I then only check if the required value is available in that package and still need to enter BOM info at symbol selection time)


(OT: there’s a strange bug in this forum software, I don’t have “Reply” button in Sprig’s last post, it has “Edit” instead.)

Hmm, Am I sure I can by a resistor in 0402 package…? :thinking:


Click the 3 dots and you should get a button that looks like an arrow if it is not already there. (the huge button with reply written next to it does indeed not seem to exist for it. Not sure why)
Edit: It was marked as a wiki post. This is why it then mainly shows the edit button.


Maybe Sprig chose “Make wiki” by accident?


Ok, yeah. I had initially created the C_X7R_402, but then realized that what I really meant was to create a symbol for a 402 decoupling capacitor — that it happens to almost inevitably be an X7R, fine; but that’s not the important defining feature (as in, no, I don’t want the symbol to distinguish that I’m using an X7R vs. an X5R, etc.). My symbol is now called C_decoupling_402. The important part is that it is a decoupling capacitor with the vias to the GND and power planes already in place.

And definitely, I want to make a distinction for different sizes: I’m actually tempted to redefine all library footprints, if only to make the silkscreen text proportional to the component size!!! That may well be the #1 most annoying aspect when working with KiCAD: having 402 components where the silkscreen text is 1.5× the size of the part’s courtyard. Anyway, it’s all part of saving on the repetitive work associated to most layouts.

(BTW, I’m a “he”, so you can feel free to refer to me as “him / his”)