Footprint with electrically connected pins

I am creating a footprint where the copper is on F.Cu and B.Cu with a rectangular pin directly above the other. The top and bottom pins are both the same number in my case.

At fabrication an electrical connection will be made to both top and bottom.

Everything works except routing in freerouting… where the top and bottom pin are considered to not be electrically connected. I can work around this by placing a via in the centre of each pin pair but I don’t really want the vias in the final board, instead I am happy to rely on the external connection between top and bottom.

Is there anyway in the footprint to give pad a number and say it is electrically connected to the pad with the same number?

That’s not my experience. If the pads are in the same net, freeRouting will connect them. Have you checked with the Highlight Net tool? In both eeschema and pcbnew?

I tried to simplify…

So I have my single socket with two pairs of pins connected and everything else disconnected…

I create a PCB…

Note: All the pins have X next to them… which I had not noticed before…

Then a quick bit of manual routing…

Then if you run DRC…

so Pads top and bottom are definitely not connected

I can bodge by adding vias…

I think that this is nothing to do with Spectra… The footprint has pin 1 (and the rest) on FCu and BCu and they are in the same net but they are not electrically connected so if only one side is wired then the other side remains unsatisfied; this is why Spectra struggles with my (very constrained) design since it tries to wire up FCu AND BCu whereas I know that FCu and BCu are electrically connected externally…

… so I guess I need a way to tell the footprint that FCu Pad 1 and BCu Pad 1 are not only in the same net but they are also already connected??

So let me get this straight: You have F and B pads which have the same pad number but they don’t have plated through holes? Are you expecting the IC pin to act as a conductive through hole? In theory as they have the same pin number, there should be a vertical rats nest line between F and B, and freeRouting should create a trace between the F and B, but I wonder if this is an edge condition where it fails because the coordinates are the same or it believes you have a PTH.

Yes that’s correct. Along the edges I have pins like these…

So once the pins have been connected to the assembly the top and bottom pads will be connected electrically via the pin material. (Very like having plated through holes that you mentioned)

My problem is that routing to a pad on one side doesn’t satisfy the other side. There isn’t a PTH… and since there isn’t FreeRouting thinks they are distinct. I noticed this because my design is so space constrained there isn’t sufficient space to route both top and bottom to the remaining circuit.

Adding vias is a workaround since this satisfies the connection between FCu and BCu.

Ok, so you don’t expect anything more from freeRouting, but you are concerned about the DRC? You could ignore those warnings.

Is there a reason you avoid PTH?

Sorry… my edit overlapped with your reply…

I hope that the footprint could tell FreeRouting that the Pad on FCu was connected to BCu even though in this case there is no PTH. i.e. the effect of a PTH without a PTH?? (or the effect of a VIA without a VIA)

So you were hoping that freeRouting would create a via and satisfy the DRC? But if it created vias next to the pads it would look ugly, so maybe the DRC errors are the lesser evil to the freeRouting bug. Why not just use PTHs? No harm wearing belts and braces.

So you were hoping that freeRouting would create a via and satisfy the DRC?

Absolutely not! I don’t want or need vias or PTH. And I certainly don’t want freerouting to automagically create anything.

But if it created vias next to the pads it would look ugly, so maybe the DRC errors are the lesser evil to the freeRouting bug.

I need a way to indicate that FCu and BCu pads are electrically connected; that way freerouting will satisfy both by routing to either

Why not just use PTHs? No harm wearing belts and braces.

I don’t need holes. I need the effect of PTH without a hole!

Is this a home etching or a milled project? If it is a commercially made PCB, there is no reason to avoid PTH and they make the pads much less likely to lift off the PCB when soldered

It’s commercial. (Do people really bother with home boards anymore?!?)… anyway…it’s actually in manufacturing at this very moment and I worked around the problem by putting a via on every pad pair. Given a via is really a very small plated through hole then maybe that is the workaround… Create a footprint with a via sized PTH on each pad pair.
That is a workaround though… since the PTH/Via is not required iff I rely on the external connection provided by the subsequent pin assembly.
I imagine that somewhere in the internals the fact that a PTH exists must create an electrical connection between FCu and BCu (and other Cu layers) and this feeds into DRC… that’s the effect I want… without a hole!! :grinning:

Well having the same pin number doesn’t indicate that they are already connected internally or in some other way, or not. It just puts them in the same net and the trace still has to be created. It seems freeRouting failed to do this. If it had succeeded, you would not have liked the result.

Here’s a switch on a circuit board. Internally the pins 1 and 2 are connected, but freeRouting still created the traces between the 1s and the 2s. Which is what was wanted, even though one of each pair would have sufficed.


Exactly. But in my case the board proved un-routable because it is so small/dense that there isn’t space for the unnecessary traces. That’s where the freeRouting issue comes in. By adding vias it becomes feasible… horrid but feasible.

So in your example… wouldn’t it be nice to be able to express that 1 and 1 were magically connected and did not need to be routed?

Maybe, but I don’t have a use case for that.

And you would need an additional attribute beyond pin number.

I do. :grinning: In fact I am using 4 layers and it is still pretty much impossible to fit the unnecessary traces in. (Everything has to fit in width : 15mm height : 35mm)

(pad 1 thru_hole rect (at 0 0) (size 1.3 1.6) (drill 1) (layers *.Cu *.Mask)  (net 8 "Net-(U2-Pad1)"))

(pad 2 smd rect (at 0 2.54) (size 1.3 1.6) (layers B.Cu B.Paste B.Mask) (net 7 “Net-(U2-Pad16)”))

thru_hole must imply some electrical connection magic that smd does not; sady a thru_hole with a drill size of zero… i.e. no hole isn’t possible.

It is not possible to tell KiCad that the pins are externally connected.

So route the pcb knowing it and be aware there will be a non-connected DRC error. Then ignore the error.
Or put a via connecting both pins, finish the routing, delete the via and ignore the unconnected error. If the pins are actually connected outside the board, the electrons will ignore the unconnected error too :wink:

For manual routing that is fine. But that approach doesn’t work when using freeRouting (spectra).

The workaround is to place VIAs, route in freeRouting, then delete the VIAs and ignore the subsequent DRCs but that doesn’t work well for a series of changes during the design lifecycle… in fact it is a PIA and I was so sick of deleting and re-creating VIAs that I started this thread. :grinning:

I had a quick look at the code around “smd, thru_hole, np_thru_hole and connect” and it looks like I really just want a thru_hole without a drill. But given drill size zero is expressly forbidden (for no apparent reason) I’ll hold off creating my own branch. :upside_down_face:

But what you were asking for is a contradiction in terms. You wanted freeRouting to make them connected without creating a via. The problem goes back to that there’s no way to tell DRC they are already connected elsehow. You want a different beast, a pad that where F and B are connected but there’s no hole or plating.

And why can’t I have one! Call it a “connect_double_sided” or a “thru_hole_without_hole”…whatever. But that’s exactly what I want! :grinning:

That would violate the principle of documented cause for effect. The property of that beast relies on something that is not expressed in the schematic, an external connection. You could give the F and B pads distinct numbers and draw the external connection in the schematic.