I’ve got a schematic I’m attempting to transition to a PCB layout. A primary feature of the circuit is a pair of connectors, J1, a female (designated VSF), and its mate J2 (designated VSM). I have good footprints for both. Another relevant feature is that there are supposed to be connections between every assigned pin on J1 to its counterpart on J2, 200 pins on each connector, arranged as individual sub-parts for each row of 20 pins, designated A through K.
Unfortunately, when I send the schematic to PCB, although J2 is populated, no rats nest connections are being made to it. Inspection of J2 part via the Symbol Properties dialog show that its Library Link field incorrectly points to J1. I’ve tried correcting this error by right clicking the errant part in question, selecting Update Symbol, and redirecting to the correct link in the Update Symbols Matching Library Identifier (which shows the incorrect J1/VSF pointer) to the proper VSM target. But when I press the Update button, the message returned indicates the symbols was incorrectly redirected (again) to the VSF connector.
As an alternate tactic, I tried using the Update Symbols from Library command. Again, the Update symbols matching library identifier points to the incorrect VSF link. Using the symbol chooser button, I reselect the proper VSM link, but again, when I hit OK, the output message indicates it has been reset to the improper VSF file.
This error is not uniform across the entire array of J2 subparts. Indeed, when I try the Symbol Library References dialog, J2 shows up twice, both under the VSF and VSM parts. So, it looks like to me some bad links have slipped into the data file, and are pointing to multiple sources for a single connector. I suspect that the PCB program can’t finish its rats nest connections because of this confusion. Can anyone please offer any suggestions on how I might flush out this corruption so I can proceed with PCB generation? Many thanks for any assists!
Followup: Had better luck using Change Symbol, rather than Update Symbol. At least, this change did not seem to be rejected the way Update was. However, this did not resolve the problem about the parts arriving in the PCB without the expected rats nest connection lines.
A few things unclear here. Connectors do no mate very well when they are soldered to the same PCB. Do you have two projects, or are you creating some kind of panel that is to be broken in sections?
For KiCad, it’s the J1 and J2 that determine which symbol is used, and one symbol (which can have units A through Z, maybe more, translates to one footprint.
That Library link points to a schematic symbol. Both your male and female connectors can use the same schematic symbol. There is nothing inherently wrong with that.
While I was typing, you found the Change Symbol button, which can be used to change the graphics of a symbol, and apparently it worked, so I’ll consider that fixed.
For the rest. I’m not sure what the problem is.
Does ERC complain about anything (relevant)?
Does cross probing between PCB and schematic work for symbols / footprints?
Can you share this project? (It’s always much easier do diagnose from the project itself).
Clarification: My assignment is to build a test board. There are two Units to be Tested (UUTs) that mate to one another via this pair of connectors. We pull those UUTs apart, and insert my test board in between. So I need each one of each gender to pick up the UUTs in question, so my Test board has both genders.
I may have been unclear in my description, but yes, I believe my understanding matches KiCad’s use of symbols and footprints, at least in application to this part. Each part has a single RefDes (e.g. J1 and J2), but each part uses 10 symbols to present 20 pin rows A-K (skipping I). Each part (VSM, and VSF) has its own footprint, similar but mirrored allowing them to mate. As far as I can tell, the footprints represent the hardware.
ERC is down to a single warning, telling me about that missing and unassigned “I” symbol, but that was skipped on purpose, and I’ve not found a way to tell KiCad that’s on purpose.
Cross Probing: Seems to work. I can confirm the connections I intended between J2/VSM and an RJ-45 jack on the board; and yet no rats net connection shows up to reflect that. I will note that the PCB highlights/selects the RJ-45 when I probe this connection (though J2/VSM does not). Other RJ-45’s connected to J1/VSF show up in the PCB as expected, and probes highlight their rats nest connections.
Sharing the Project: Wish I could, but I’ll have to ask permission. My board is trivial, but the UUTs involved are less so, and I’ve used signal names from the UUTs. Maybe if I scrub some of the signal names I could do so. Stand by.
You can scrub most of the stuff. Just the connectors and about a handful of wires from them connecting to “something” in the project is enough.
Maybe you can even replicate your problem with for example a COTO3602_SPLIT and a COTO_3650_Split as placeholders for your connectors.
But there is some work involved in creating a test project from that.
It’s also possible you find the error while creating such a (simplified) test project.
OK, so I threw together a schematic using the same parts, tossed in a bus, and a dozen or so connections. Then I sent them to PCB to see what happened. I took care to connect the same set of signals on both J1 and J2 parts via the Mainbus. The result mirror what happened in my project - there are no connections indicated to either J1 or J2, or the J3 jack connected directly to J2. I included jack J4 also connected to a subset of signals. These last signals are the only ones that appear in the PCB rats nest.
Now I had a big laugh. No offense meant of course.
If you have a symbol pin with name A1, then it does not connect to a footprint pin with the pad name 1A.
To be unambiguous: don’t swap the letters and numbers.
I guess you get that for staring at your project from too close for too long.
No offense taken - you’ve provided a lot of help, so for pointing out something so obvious, you certainly deserve a good laugh at the very least.
Now I’ve got a well-defined task of modifying 200 pin designators. I can’t even remember how I arrived at that pattern numbering, save that KiCad’s autonumbering system (as I recall) forced me into that number-first config. I guess I must have manually changed them on one connector but not the other.
No. Don’t change the pins. Pin names are the same for the two connectors.
It is the pad names in the footprints that have different ordering. Also, pad arrays have a quite elaborate numbering scheme built in. You can just draw a single big array of pads. The array pad number even has the option to skip the IOSQXZ letters.
That’s me being imprecise with my wording again. I got that it was the footprint pads that were in error. Perhaps it could be done more quickly by creating a new pad array, but as I recall, that may have been what bit me in the first place - I found no provision in the tool for placing the letters in front of the numbers.
In any event, it seemed easier to manually edit the pad designators.
It worked for me with the settings shown in the screenshot. There are lots of settings there. take note of the “primary axis numbering” and “Pad numbering start” with “A1”. You may have to experiment a bit with these settings to get familiar with them.
You can also always use a text editor to modify symbols or footprints. Especially when using regular expressions editing like this can be done very effectively.
